Maximum Allowable External As_Data Pin Skew Delay Guidelines - Intel Agilex Series Configuration User Manual

3. Intel Agilex Configuration Schemes
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Figure 41. AS Configuration Serial Input Timing Diagram
Table 34.
T as a Function of
ext_delay
Symbol
T
ext_delay
Note: For more information about the timing parameters, refer to the Intel Agilex Device Datasheet.

3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines

You must minimize the skew on the AS data pins.
Send Feedback
nCSO
AS_CLK
T
ext_delay
AS_DATA IN0
Frequency
AS_CLK
Configuration Clock Source
Internal Oscillator
OSC_CLK_1
IN1 INn
Frequency Min (ns)
115 MHz
77 MHz
58 MHz
25 MHz
166 MHz
125 Mhz
100 MHz
71.5 MHz
50 MHz
25 MHz
Max (ns)
0 20
0 20
0 20
0 24
0 13.5
0 18
0 24
0 35
0 24
0 24
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