Intel Agilex Series Configuration User Manual page 77

3. Intel Agilex Configuration Schemes
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Figure 26. Process for Using the PFL IP Core
Figure shows the process for using the PFL IP core, using MAX II as an example.
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Intel Agilex F-Series Transceiver-SoC Development Kit
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Create a new MAX II design,
instantiate the PFL Megafunction in
the MAX II design, and create
Pin Assignments
Compile
and obtain
MAX II
.pof
Add the MAX II .pof to the
Quartus Prime Programmer
Add the flash .pof in the
Quartus Prime Programmer
Program the MAX II and Flash Devices
MAX II configures the FPGA with the
configuration data from the Flash Device
Create new FPGA
designs
Compile and
obtain the
FPGA
.sof(s)
Add the .sof(s) for conversion to .pof
Convert to
.pof for the
Targeted
Flash
Create the optional Jam
programming file
Intel ® Agilex ™ Configuration User Guide
77