Intel Agilex Series Configuration User Manual page 8

The JTAG port has the highest priority and overrides the
device over JTAG even if the
CvP
CvP uses an external PCIe* host device as a Root Port to configure the Intel Agilex device over the PCIe link. You can specify
up to a x16 PCIe link. Intel Agilex devices support two CvP modes, CvP initialization and CvP update.
Note: Typically, the data rate of the device's internal configuration data path, not the PCIe link width, limits the configuration data
rate. The maximum data rate depends on the PCIe generation and number of lanes.
CvP initialization process includes the following two steps:
1. During the board power up, the CvP uses quad SPI memory in AS x4 mode to configure the FPGA with the periphery
image to enable CvP interface that includes the PCIe IP. The PCIe link training establishes the PCIe link of the CvP PCIe IP
before the core fabric configures.
2. The host device uses the CvP PCIe link to configure your design in the core fabric.
CvP update mode updates the FPGA core image using the PCIe link already established from a previous full chip configuration
or CvP initialization configuration. After the Intel Agilex enters user mode, you can use the CvP update mode to reconfigure
the FPGA fabric. This mode has the following advantages:
• Allows to change core algorithms logic blocks.
• Provides a mechanism for standard updates as a part of a release process.
• Customizes core processing for different components that are part of a complex system.
For Intel Agilex SoC devices, CvP is only supported in FPGA configuration first mode.
AS Normal Mode
Active Serial x4 or AS x4 or Quad SPI is an active configuration scheme that supports flash memories capable of three- and
four-byte addressing. Upon power up, the SDM boots from a boot ROM which uses three-byte addressing to load the
configuration firmware from the Quad SPI flash. After the configuration firmware loads, the Quad SPI flash operates using
four-byte addressing for the rest of the configuration process.
Intel ® Agilex ™ Configuration User Guide
8
MSEL
pins specify a different configuration scheme unless you disabled JTAG for security reasons.
MSEL
1. Intel
pin settings. Consequently, you can configure the Intel Agilex
® ™
Agilex Configuration User Guide
683673 | 2021.10.29
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