Intel Agilex Series Configuration User Manual page 83

3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Pin
flash_nreset
fpga_nconfig
pfl_reset_watchdog
pfl_watchdog_error
Related Information
Avalon Interface Specifications
3.1.7.3. Generating the PFL II IP Core
3.1.7.3.1. Controlling Avalon-ST Configuration with PFL II IP Core
The PFL II IP core in the host determines when to start the configuration process, read the data from the flash memory
device, and configure the Intel Agilex device using the Avalon-ST configuration scheme.
Figure 27. FPGA Configuration with Flash Memory Data
Send Feedback
Type Weak Pull-Up
Output —
Open Drain Output 10-kW Pull-Up
Resistor
Input —
Output —
Host
Avalon-ST
PFL II
Flash
Interface
Flash
Memory
Function
Connects to the reset pin of the flash memory device. A low signal resets
the flash memory device.
Connects to the pin of the FPGA. A low pulse resets the FPGA
nCONFIG
and initiates configuration. These pins are not available for the flash
programming option in the PFL II IP core.
A switch signal to reset the watchdog timer before the watchdog timer
times out. To reset the watchdog timer hold the signal high or low for at
least two clock cycles.
pfl_clk
When high indicates an error condition to the watchdog timer.
Intel FPGA
Intel
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® Agilex ™ Configuration User Guide
83