Advantech AMAX-5000 Series User Manual page 165

Thus, shortening the EtherCAT cycle time is required for both scenarios. But most of
the time, the limitation of the EtherCAT cycle time is restricted by the number of slave
devices and the total data length of the PDOs and also, the minimum cycle times of
the EtherCAT protocol which is about 100µs. Furthermore, shortening the EtherCAT
cycle time will also increase the load of the master controller since the data acquisi-
tion frequency is increased; the system resource will be occupied by the data acquisi-
tion tasks. Therefore, a time-stamping function for digital IO modules has been
designed for these advance applications.
7.1.2 The EtherCAT data transfer in time base
Benefiting from the EtherCAT distributed clock mechanism, all EtherCAT slave
devices are able to synchronize to master controller's system time in a 64-bits time-
stamp value with a resolution of 1ns. (The timestamp format is starting from 1.1.2000
00:00)
Figure 7.3 EtherCAT Distributed Clock
The time-stamped digital input/output signal transfers data via the EtherCAT bus,
which makes the data exchange more precise and easier from the PLC cycle.
Digital Input with Timestamp
In order to latch the input signal, the digital input module contains a set of parameters
to record the precise timestamp for each rising-edge (th) and falling-edge (tl).
One thing to be noticed, is that there is only one set of timestamp can be stored in the
module, so the user should select the latching mode: Single Event or Continuous
(default).
The Single Event mode only latches the first rising-edge and falling-edge timestamp
and ignores any state change afterward. The Continuous mode will continuously
update the latest timestamp of state change.
Each rising-edge (th) and falling-edge (tl) can be set to Single Event mode or Contin-
uous mode independently.
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