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Specifications
A.7.2
CMM Slot P2 Interface
Table 33
1
Table 33. P2 Connector CMM Pin Assignments
Pin #
11
10
9
8
7
6
5
4
3
2
1
1. In the ZT 5085 midplane, N_SCL1 and N_SDA1 signals are not used because the CMMs are in slot 1.
2. The CompactPCI* specifications define the IPMB signals as bused. Intel systems that implement CMM
slots route slot-specific IPMBs to the CMM(s) in a star topology. The IPMB in slot n is connected to the
N_SCLn and N_SDAn signals on the CMM(s).
A.7.3
CMM Slot P3 Interface
Table 35
Table 35. P3 Connector CMM Pin Assignments (Sheet 1 of 2)
Pin #
11
10
9
8
7
6
5
4
3
2
1
90
specifies the P2 interface for CMM slots .
Z
A
1
GND
N_SCL1
2
GND
N_SCL2
2
GND
N_SCL3
2
GND
N_SCL4
2
GND
N_SCL5
2
GND
N_SCL6
2
GND
N_SCL7
2
GND
N_SCL8
2
GND
N_SCL9
GND
R_SCL
IPMB_PWR
GND
GND
specifies the P3 interface for CMM slots.
Z
A
1
GND
N_HLY1#
N_BDS1#
2
GND
N_HLY2#
N_BDS2#
2
GND
N_HLY3#
N_BDS3#
2
GND
N_HLY4#
N_BDS4#
2
GND
N_HLY5#
N_BDS5#
2
GND
N_HLY6#
N_BDS6#
2
GND
N_HLY7#
N_BDS7#
2
GND
N_HLY8#
N_BDS8#
2
GND
N_HLY9#
N_BDS9#
GND
RES
GND
IPMB_PWR
B
C
1
2
N_SDA1
N_SCL10
2
2
N_SDA2
N_SCL11
2
2
N_SDA3
N_SCL12
2
2
N_SDA4
N_SCL13
2
2
N_SDA5
N_SCL14
2
2
N_SDA6
N_SCL15
2
2
N_SDA7
N_SCL16
2
2
N_SDA8
N_SCL17
2
N_SDA9
GND
3
RES
R_SDA
CMM_SEL#
B
C
1
2
N_HLY10#
3
2
N_HLY11#
3
2
N_HLY12#
3
2
N_HLY13#
3
2
N_HLY14#
3
2
N_HLY15#
3
2
N_HLY16#
3
2
N_HLY17#
3
IPMB_PWR
GND
RES
RES
PRES_O#
D
E
2
N_SDA10
N_SCL18
2
N_SDA11
N_SDA18
2
N_SDA12
N_SCL19
2
N_SDA13
N_SDA19
2
N_SDA14
N_SCL20
2
N_SDA15
N_SDA20
2
N_SDA16
N_SCL21
2
N_SDA17
N_SDA21
NEG_O
HLY_O#
3
IPMB_PWR
HLY_I#
NEG_I
GND
D
E
3
2
N_BDS10#
N_HLY18#
3
N_BDS11#
N_BDS18#
3
2
N_BDS12#
N_HLY19#
3
N_BDS13#
N_BDS19#
3
2
N_BDS14#
N_HLY20#
3
N_BDS15#
N_BDS20#
3
2
N_BDS16#
N_HLY21#
3
N_BDS17#
N_BDS21#
RES
RES
GND
RES
RES
IPMB_PWR
Technical Product Specification
F
2
GND
2
GND
2
GND
2
GND
2
GND
2
GND
2
GND
2
GND
GND
GND
GND
F
GND
3
GND
GND
3
GND
GND
3
GND
GND
3
GND
GND
GND
GND
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