Standard Fabric Slot P3/P4/P5 Interfaces; Standard Fabric Board P3 Pin Assignments - Intel NetStructure ZT 5085 12U Manual

A.6.5

Standard Fabric Slot P3/P4/P5 Interfaces

Table 26,
for midplane Ethernet channels. P4 is used for rear panel I/O. There are no deviations from the
specification for these interfaces except that each fabric slot has one Ethernet channel routed to a
CMM. Refer to the PICMG*2.16 R1.0 specification for more information.
Table 26. Standard Fabric Board P3 Pin Assignments
Pin #
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NOTE: GND for Type B style J3 connector.
Technical Product Specification
Table 27 and Table 28 specify the interfaces for standard fabric slots. P3 and P5 are used
Z A
GND SGA4
GND LPf_DA+ LPf_DA-
GND LPf_DB+ LPf_DB-
GND LP8_DA+ LP8_DA-
GND LP8_DB+ LP8_DB-
GND LP7_DA+ LP7_DA-
GND LP7_DB+ LP7_DB-
GND LP6_DA+ LP6_DA-
GND LP6_DB+ LP6_DB-
GND LP5_DA+ LP5_DA-
GND LP5_DB+ LP5_DB-
GND LP4_DA+ LP4_DA-
GND LP4_DB+ LP4_DB-
GND LP3_DA+ LP3_DA-
GND LP3_DB+ LP3_DB-
GND LP2_DA+ LP2_DA-
GND LP2_DB+ LP2_DB-
GND LP1_DA+ LP1_DA-
GND LP1_DB+ LP1_DB-
B C
SGA3 SGA2
GND LPf_DC+
GND LPf_DD+
GND LP8_DC+
GND LP8_DD+
GND LP7_DC+
GND LP7_DD+
GND LP6_DC+
GND LP6_DD+
GND LP5_DC+
GND LP5_DD+
GND LP4_DC+
GND LP4_DD+
GND LP3_DC+
GND LP3_DD+
GND LP2_DC+
GND LP2_DD+
GND LP1_DC+
GND LP1_DD+
Specifications
D E
SGA1 SGA0
LPf_DC-
LPf_DD-
LP8_DC-
LP8_DD-
LP7_DC-
LP7_DD-
LP6_DC-
LP6_DD-
LP5_DC-
LP5_DD-
LP4_DC-
LP4_DD-
LP3_DC-
LP3_DD-
LP2_DC-
LP2_DD-
LP1_DC-
LP1_DD-
F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
83