Cmm Slot P1/P2/P3 Interfaces; Cmm Slot P1 Interface - Intel NetStructure ZT 5085 12U Manual

Redundant host packet switched platform
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A.7

CMM Slot P1/P2/P3 Interfaces

A.7.1

CMM Slot P1 Interface

Table 32
Table 32. P1 Connector CMM Pin Assignments
Pin #
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NOTES:
1. The midplane routes the PINH[0-3]#, PDEG[0-3]#, PFAIL[0-3]#, PS_SCL0, and PS_SDA0 signals to the
first power tray.
2. The midplane routes the PINH[4-7]#, PDEG[4-7]#, PFAIL[4-7]#, PS_SCL1, and PS_SDA1 signals to the
second power tray. PDEG[4-7]# from the CMM(s) correspond to PDEG[0-3]# on the power tray
respectively. PFAIL[4-7]# from the CMM(s) correspond to PFAIL[0-3]# on the power tray respectively.
PINH[4-7]# from the CMM(s) correspond to PINH[0-3]# on the power tray respectively.
3. The midplane routes the FANP0#, PANPWM0, and FANTK[0-2] signals to the first fan tray.
4. The midplane routes the FANP1#, PANPWM1, and FANTK[3-5] signals to the second fan tray. FANTK[3-5]
from the CMM(s) correspond to FANTK[0-2] on the fan tray respectively.
5. The midplane routes the FANP2#, PANPWM2, and FANTK[6-8] signals to the third fan tray. FANTK[6-8]
from the CMM(s) correspond to FANTK[0-2] on the fan tray respectively.
6. The FANP3#, PANPWM3, and FANTK[9-15] signals are not used in the ZT 5085 system.
7. Because the ZT 5085 system has multiple power domains and multiple V(I/O) settings, the midplane
connects the CMM's V(I/O) pin to 3.3 V.
Technical Product Specification
specifies the P1 interface for CMM slots numbers.
Z
A
1
GND
PDEG0#
1
GND
PDEG1#
1
GND
PFAIL0#
1
GND
PFAIL1#
1
GND
PINH0#
1
GND
PINH1#
1
GND
PS_SCL0
2
GND
PS_SCL1
GND
FT_SCL
GND
CS_SCL
GND
CF_SCL0
GND
CF_SCL1
GND
RES
GND
RES
GND
STx
GND
SCTS
GND
SDSR
GND
RPMAC#
GND
RPCR#
GND
BP_5V
GND
SwTx+
GND
SwRx+
B
C
1
PDEG2#
GND
1
8
PDEG3#
IPMB_PWR
1
PFAIL2#
GND
1
8
PFAIL3#
IPMB_PWR
1
PINH2#
GND
1
8
PINH3#
IPMB_PWR
1
PS_SDA0
GND
2
PS_SDA1
RES
FT_SDA
GND
CS_SDA
RES
CF_SDA0
GND
CF_SDA1
RES
PI_SDARE
GND
S
ARES
RES
SRx
SRI
SRTS
SCD
SDTR
RES
RPMIC#
RES
RPMAR#
RPMIR#
BP_N12V
BP_12V
SwTx-
GND
SwRx-
GND
Specifications
D
E
2
2
PDEG4#
PDEG6#
2
2
PDEG5#
PDEG7#
2
2
PFAIL4#
PFAIL6#
2
2
PFAIL5#
PFAIL7#
2
2
PINH4#
PINH6#
2
2
PINH5#
PINH7#
PRES_I#
GA0
3
5
FANP0#
FANP2#
4
FANP1#
FANP3#
3
5
FANPWM0
FANPWM2
4
FANPWM1
FANPWM3
3
5
FANTK0
FANTK8
3
6
FANTK1
FANTK9
3
6
FANTK2
FANTK10
4
6
FANTK3
FANTK11
4
6
FANTK4
FANTK12
4
6
FANTK5
FANTK13
5
6
FANTK6
FANTK14
5
6
FANTK7
FANTK15
7
BP_3.3V
V(I/O)
RpTx+
RpTx-
RpRx+
RpRx-
F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
89

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