Table of Contents
Advertisement
Specifications
A.6.2
Peripheral Slot P1/P2 Interfaces
This section defines the P1/P2 interface for peripheral slots.
A.6.2.1
Peripheral Slot P1 Interface
Table 21
PICMG* 2.0 R3.0 and PICMG 2.16 R1.0 specifications. Refer to the PICMG specifications for
more detail. Exceptions are noted below the table.
Table 21. CompactPCI* Peripheral Slot P1 Pin Assignments
Pin #
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NOTES:
† The JTAG signals (TCK, TMS, TDO, and TDI) are not routed on the backplane.The JTAG signals (TCK,
TMS, TDO, and TDI) are not routed on the backplane.e JTAG signalsThe JTAG signals (TCK, TMS, TDO,
and TDI) are not routed on the backplane.The JTAG signals (TCK, TMS, TDO, and TDI) are not routed on
the backplane.The JTAG signals (TCK, TMS, TDO, and TDI) are not routed on the backplane.
78
specifies the P1 interface for the peripheral slots. The interface is in accordance with the
Z
A
GND
5 V
REQ64#
GND
AD[1]
GND
3.3 V
GND
AD[7]
GND
3.3 V
GND
AD[12]
GND
3.3 V
GND
SERR#
GND
3.3 V
IPMB_SCL
GND
DEVSEL#
GND
3.3 V
FRAME#
GND
(KEY)
GND
(KEY)
GND
(KEY)
GND
AD[18]
GND
AD[21]
GND
C/BE[3]#
GND
AD[26]
GND
AD[30]
GND
REQ#
GND
BRSVP1A5
BRSVP1B5
GND
IPMB_PWR
HEALTHY#
GND
INTA#
†
GND
TCK
GND
5 V
B
C
ENUM#
5 V
V(I/O)
AD[4]
AD[3]
GND
3.3 V
AD[9]
AD[8]
GND
V(I/O)
AD[15]
AD[14]
GND
3.3 V
IPMB_SDA
GND
V(I/O)
IRDY#
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
AD[17]
AD[16]
GND
3.3 V
IDSEL
AD[23]
GND
V(I/O)
AD[29]
AD[28]
3.3 V
PCI_RST#
V(I/O)
INTB#
INTC#
5 V
TMS
-12 V
TRST#
D
E
3.3 V
5 V
AD[0]
ACK64#
5 V
AD[2]
AD[6]
AD[5]
M66EN
C/BE[0]#
AD[11]
AD[10]
GND
AD[13]
PAR
C/BE[1]#
GND
PERR#
STOP#
LOCK#
BD_SEL#
TRDY#
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
(KEY)
GND
C/BE[2]#
AD[20]
AD[19]
GND
AD[22]
AD[25]
AD[24]
GND
AD[27]
CLK
AD[31]
GND
GNT#
INTP
INTS
5 V
INTD#
†
TDO
TDI
+12 V
5 V
Technical Product Specification
F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Advertisement
Table of Contents
