Node Slot P3 Interface - Intel NetStructure ZT 5085 12U Manual

Specifications
A.6.4

Node Slot P3 Interface

Table 25
this interface. Note, however, that rows 14 and 19 are defined as BP(I/O), but have special isolation
and/or slew rate limitations. Refer to the PICMG 2.16 R1.0 specification for more information.
Table 25. Node Slot P3 Pin Assignments
Pin #
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NOTES:
1. BP(I/O) connects front card to rear card and does not connect to backplane.
† GND for type B style J3 connector.
82
specifies the P3 interface for node slots. There are no deviations from the specification for
Z A
†
GND BP(I/O) BP(I/O)
GND LPa_DA+ LPa_DA-
GND LPa_DB+ LPa_DB-
GND LPb_DA+ LPb_DA-
GND LPb_DB+ LPb_DB-
†
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
2 1
BP(I/O) BP(I/O)
2 1
BP(I/O) BP(I/O)
2 1
BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
1
GND BP(I/O) BP(I/O)
B C
† †
BP(I/O)
GND
GND
GND
GND
† †
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
1 1
BP(I/O)
D E
† †
BP(I/O) BP(I/O)
LPa_DC+ LPa_DC-
LPa_DD+ LPa_DD-
LPb_DC+ LPb_DC-
LPb_DD+ LPb_DD-
† †
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
1 1
BP(I/O) BP(I/O)
Technical Product Specification
F
GND
GND
GND
GND
GND
GND
GND
GND
2
2
2
GND
GND
GND
GND
GND
GND
GND
GND