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Intel NetStructure ZT 5504 Manual

System master processor board
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  Summary of Contents for Intel NetStructure ZT 5504

  • Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
  • Page 2 ® ™ Intel NetStructure ZT 5504 System Master Processor Board Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 3 Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
  • Page 4: Table Of Contents

    Contents Tables .................................. 8 Figures................................. 9 Manual Organization ............................10 1. Introduction..............................11 Product Definition ............................11 Features..............................12 Functional Blocks............................14 CompactPCI/PSB Architecture......................14 Processor ............................. 15 Chipset ..............................15 PCI-to-PCI Bridge (P2P) ........................15 Memory and I/O Addressing......................... 16 Drone Mode............................
  • Page 5 Contents Unpacking..............................23 System Requirements ..........................23 BIOS Version............................23 Connectivity ............................23 Electrical and Environmental........................ 24 Memory Configuration ..........................25 I/O Configuration............................28 Connectors ..............................28 Switches and Cuttable Traces........................28 BIOS Configuration Overview........................28 Operating System Installation........................29 3.
  • Page 6 Contents BMC LED Control ..........................42 Field Replaceable Unit Information ...................... 42 System Event Log Information ......................42 SMBus Address Map ..........................42 6. IDE Controller ..............................44 Features of the IDE Controller........................44 Disk Drive Support............................. 44 Primary IDE Channel..........................44 Secondary IDE Channel........................
  • Page 7 D. Datasheet Reference ............................ 78 Board Serial Number ..........................78 CompactPCI .............................. 78 Ethernet ..............................78 Intel 440GX AGPset ..........................78 Mobile Pentium III Processor - M in BGA2 Package................. 79 PCI-To-PCI Bridge............................. 79 PMC Specification ............................. 79 SuperI/O ..............................79 Video................................
  • Page 8 Contents CE Certification............................80 Safety................................. 80 Emissions Test Regulations ........................80 EN 50081-1 Emissions ......................... 80 EN 55024 Immunity ..........................80 Regulatory Information ..........................81 FCC (USA) ............................81 Industry Canada (Canada) ........................81 F. Customer Support ............................82 Technical Support and Return for Service Assistance ................82 Sales Assistance ............................
  • Page 9: Tables

    Tables Revision History..............................2 Fault Current Limits ............................17 Switch Cross-Reference Table.......................... 31 Cuttable Trace Definitions ..........................35 Connector Assignments ............................ 56 J1 CompactPCI Bus Connector Pinout ......................58 J2 CompactPCI Bus Connector Pinout ......................59 J3 Connector Pinout ............................60 J5 Rear Panel I/O Connector Pinout .........................
  • Page 10: Figures

    Figures ZT 5504 Faceplate ............................12 Functional Block Diagram..........................14 Memory Address Map Example ........................26 I/O Address Map..............................27 Setup Screen..............................29 Default Switch Configuration ..........................32 Cuttable Trace Locations........................... 36 Watchdog Timer Architecture..........................46 BIOS Recovery Socket Location ........................51 PCB Dimensions ...............................
  • Page 11: Manual Organization

    Manual Organization This manual describes the operation and use of the Intel® NetStructure™ ZT 5504 System Master Processor Board with a Mobile Intel® Pentium® III Processor - M. The following topics are covered in this manual. Chapter 1, "Introduction," introduces the key features of the ZT 5504. This chapter includes a product definition, a list of product features, and a functional block diagram with a brief description of each block.
  • Page 12: Introduction

    CompactPCI* system. It utilizes the Mobile Intel Pentium III Processor - M, in a BGA2 package, to provide extremely high PCI performance and the latest in memory and I/O technology combined with low power requirements.
  • Page 13: Features

    CompactPCI Specification, PICMG 2.16, Version 1.0 compliant • 6U single-slot CompactPCI form factor • Mobile Intel Pentium III Processor - M, BGA2 package • Intel® 440 GX chipset Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 14 • Dual stage watchdog timer • Intel® 69000 series AGP graphics chip • IPMI through an Intel® Baseboard Management Controller chip • Dual 10/100 Mbit/s Ethernet* (available at the faceplate or the J3 backplane connector) • Primary IDE channel supports the on-board 2.5 inch hard disk and an IDE device (CD-ROM) on a media expansion board •...
  • Page 15: Functional Blocks

    1. Introduction Functional Blocks The following topics provide overviews of the ZT 5504's main features, some of which are shown in the functional block diagram below. Functional Block Diagram PMC Slot Status Serial Ethernet B Reset USB 1 USB 0 Video LEDs Port...
  • Page 16: Processor

    Chipset The Intel 440GX AGPset consists of the 82443GX Host Bridge and the 82371EB (PIIX4E) I/O subsystem chip. The Host Bridge includes an optimized SDRAM controller. The I/O subsystem is a highly integrated PCI ISA IDE Xcelerator Bridge.
  • Page 17: Memory And I/O Addressing

    1. Introduction Memory and I/O Addressing The ZT 5504 supports 512 MB or 1 GB of local memory. This memory is installed at the factory and is not field upgradeable. The local memory is implemented as Error-Correcting Code (ECC) SDRAM. ECC will correct single bit errors (97% of all DRAM errors are single bit errors) and can report multiple bit errors to the operating system.
  • Page 18: Rear-Panel I/O

    1. Introduction Fault Current Limits Power Source Minimum Maximum +5.0V 10.0A 15.0A +3.3V 9.4A 14.1A +12V 1.0A 1.5A -12V 0.6A 0.9A Notes: • The fault trip currents listed above are design values. Noisy power sources can lower the fault trip current limits to less than the minimum design values.
  • Page 19: Pci Mezzanine Card (Pmc) Interface

    The ZT 5504 provides two 10/100BaseTx Ethernet channels (A and B) through the Intel® 82550 Fast Ethernet Multifunction PCI Controller with integrated Alert On LAN (AOL). The 82550 consists of both the Media Access Controller (MAC) and the physical layer (PHY) interface combined into a single component solution.
  • Page 20: Interrupts

    • On-board PCI devices Enhanced capabilities include the ability to configure each interrupt level for active high-going edge or active low-level inputs. The ZT 5504's interrupt controllers reside in the Intel® 82371EB (PIIX4E) device. The "Intel 440GX AGPset" topic in Appendix E provides a link to the datasheet for this device.
  • Page 21: Dma

    Two enhanced, 8237-style DMA controllers are provided on the ZT 5504 for use by the on- board peripherals. The ZT 5504's DMA controllers reside in the Intel 82371EB (PIIX4E) device. The "Intel 440GX AGPset" topic in Appendix E provides a link to the datasheet for this device.
  • Page 22: Baseboard Management Controller

    1. Introduction The ZT 5504's USB channels are controlled by the Intel 82371EB (PIIX4E) device. The "Intel 440GX AGPset" topic in Appendix E provides a link to the datasheet for this device. Baseboard Management Controller The ZT 5504 includes an Intel Baseboard Management Controller (BMC) chip. The BMC provides SMBus (System Management Bus) interfaces and is IPMI (Intelligent Platform Management Interface) compliant.
  • Page 23: Software

    Amber = needs attention Software The ZT 5504 includes the Intel® NetStructure™ Embedded BIOS v5.x loaded in on-board flash. The BIOS is user-configurable to boot an operating system from local flash memory, a hard drive, CD-ROM drive, or over a network. BIOS and firmware updates can be downloaded from the Intel Website.
  • Page 24: Getting Started

    Check the shipping carton for damage. If the shipping carton and contents are damaged, notify the carrier and Intel for an insurance settlement. Retain the shipping carton and packing material for inspection by the carrier. Obtain authorization before returning any product to Intel.
  • Page 25: Electrical And Environmental

    V(I/O) in drone mode. It will not correctly terminate the PCI bus if used in a system slot configured for 3.3V V(I/O). For this reason, Intel ships the ZT 5504 with a blue key in CompactPCI connector J1, which prevents the ZT 5504 from being installed in any slot configured for 3.3V V(I/O).
  • Page 26: Memory Configuration

    2. Getting Started The ZT 5504 is supplied with a heatsink allowing the processor to operate between 0° and approximately 50°C ambient with a minimum of 200 LFM (1 meter per second) of external airflow. It is the users' responsibility to ensure that the ZT 5504 is installed in a chassis capable of supplying adequate airflow.
  • Page 27: Memory Address Map Example

    2. Getting Started Memory Address Map Example 4 GB FFF80000h - FFFFFFFFh SYSTEM BIOS/Flash 4 GB - 512 KB 8000000h - FFF7FFFFh PCI PERIPHERALS 512 MB 100000h - 1FFFFFFFh SYSTEM MEMORY 1 MB E0000h - FFFFFh SYSTEM BIOS 896 KB C8000h - DFFFFh BIOS EXTENSION 800 KB...
  • Page 28: I/O Address Map

    2. Getting Started I/O Address Map D00 - FFFFh CF8 - CFFh PCI Config/RST Control Onboard ISA peripherals addressed between 780 - CF7h PCI Reserved 100h - 7FFh decode 11 bits 778 - 77Fh LPT ECP Registers of address (A0h - A10h). 400 - 777h Reserved Therefore, these peripherals...
  • Page 29: I/O Configuration

    BIOS Configuration Overview This topic presents an introduction to the ZT 5504's BIOS. For more detailed information about the BIOS and other utilities, see the Intel NetStructure Embedded BIOS Manual available on the Intel Website. The BIOS has many separately configurable features. These features are selected by running the built-in Setup utility.
  • Page 30: Operating System Installation

    2. Getting Started Setup Screen BIOS Setup Utility Main Advanced Power Boot Diagnostics Exit Item Specific Help System Time: [13:11:02] System Date: [10/23/01] Legacy Diskette A: [1.44/1.25MB 3½"] <Tab>, <Shift-Tab>, or <Enter> selects field. Primary Master [3242 MB] Primary Slave [None] Secondary Master [None]...
  • Page 31 5. Proceed with the OS installation as directed, being sure to select appropriate device types if prompted. Refer to the appropriate hardware manuals for specific device types and compatibility modes of Intel products. 6. When installation is complete, reboot the system and set the boot device order in the SETUP boot menu appropriately.
  • Page 32: Configuration

    3. Configuration The ZT 5504 has been designed for maximum flexibility. Many features can be configured by the user for specific applications. Most configuration options are selected through the BIOS Setup utility (discussed in the "BIOS Configuration Overview" topic in Chapter 2). Some options cannot be software controlled and are configured with switches or cuttable traces.
  • Page 33: Switch Descriptions

    3. Configuration Default Switch Configuration Switch Descriptions The following topics list the switches in numerical order and provide a detailed description of each switch. SW1 (Reset) SW1 is a push-button on the front of the ZT 5504. Pressing SW1 issues a hard reset. Reset is discussed in more detail in Chapter 4.
  • Page 34: Sw2-3 (Vga Routing Control)

    3. Configuration CAUTION: Do not close SW2-1 and SW2-2 at the same time. Doing so will significantly shorten battery life. SW2-1 SW2-2 CMOS Configuration RAM Closed Open Default Normal operation - battery backed. Open Closed Clear CMOS (return to default after clearing). SW2-3 (VGA Routing Control) This switch controls the routing of VGA signals to either the front or rear of the board.
  • Page 35: Sw3-3 (Ipmi Flash Write Protect)

    Open Default Normal Operation. Closed Console redirection enabled. Refer to the "Console Redirection" chapter in the Intel NetStructure Embedded BIOS Manual before attempting to use this feature. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 36: Cuttable Trace Options And Locations

    3. Configuration Cuttable Trace Options and Locations The ZT 5504 contains several cuttable traces (zero Ω shorting resistors) that allow the user to configure certain options not configurable through the BIOS Setup Utility. The "Cuttable Trace Locations" figure shows the placement of the ZT 5504's cuttable traces. The "Cuttable Trace Locations"...
  • Page 37: Cuttable Trace Locations

    3. Configuration Description CT38 D_RSTDRV- to COM port driver CT51 Push-button reset (SW1) chassis GND to logic GND CT57 USB0- front or rear routing CT58 USB0+ front or rear routing Cuttable Trace Locations CT16 CT19 (ID 0) CT14 CT15 CT17 CT18 (VIDEO) (KBD/MS)
  • Page 38: Ct14, Ct15, Ct17-19, Ct21-24, And Ct51 (Connect Chassis Gnd To Logic Gnd)

    3. Configuration CT14, CT15, CT17-19, CT21-24, and CT51 (Connect Chassis GND to Logic GND) The ZT 5504's faceplate connectors, push-button reset, and ejectors are on an isolated chassis ground. These components can be connected to the ZT 5504 logic ground by installing the ten cuttable traces listed above.
  • Page 39: Ct38 (D_Rstdrv- To Com Port Driver)

    3. Configuration CT38 (D_RSTDRV- to COM Port Driver) Installing CT38 disables the COM port driver during board reset to prevent glitching of the RS- 232 interface as the ZT 5504 comes out of reset. The factory default installs CT36. CT38 Function Default Disable RS-232 driver during board reset.
  • Page 40: Reset

    4. Reset This chapter discusses the reset types and reset sources on the ZT 5504. If necessary, the ZT 5504's board reset characteristics can be tailored to the requirements of a specific system. Reset Types and Sources The ZT 5504's reset types are listed below. The sources for each reset type are detailed in the following topics.
  • Page 41: Backend Power Down Sources

    4. Reset Keyboard CTRL-ALT-DEL Simultaneously pressing these keys calls a BIOS function that reboots the system. This method does not work under operating systems that trap calls to this BIOS function. Watchdog Timer (System Register Address 79h) The watchdog timer may be programmed to generate a "CPU Init" if it is not strobed within a given time-out period.
  • Page 42: System Monitoring And Control

    5. System Monitoring and Control The ZT 5504 performs system control and monitoring functions using an Intel Baseboard Management Controller (BMC) ASIC. The BMC has the following features. • IPMB_PWR delivers 5VDC (1A/pin) to the BMC; other required voltages are derived from this.
  • Page 43: Bmc Led Control

    5. System Monitoring and Control Control Functions • CPU board Reset Control • CPU board power on/power off control • CPU NMI Assertion to processor • Dual Domain Mode (TBD) BMC LED Control The BMC controls the following status LED pins: LED0 FP_BMC_BLUE_LED- LED1...
  • Page 44 5. System Monitoring and Control Device ZT 5504 Function Address Ethernet B Ethernet controller B 0101 101 Field Replaceable Unit SEEPROM 1010 010 System Event Log SEEPROM 1010 011 Signal Presence Detect (SPD) PROM in Bank #1 1010 000 SDRAM Banks (1 and 2) Signal Presence Detect (SPD) PROM in Bank #2 1010 001...
  • Page 45: Ide Controller

    The ZT 5504's IDE controller provides two IDE channels for interfacing with up to four IDE devices. The IDE controller is incorporated into the Intel PIIX4E (82371EB) device, which uses the Peripheral Component Interconnect (PCI) bus to provide exceptional IDE performance. The IDE controller can sustain a maximum transfer rate of 33 Mbps between the IDE drive buffer and the PCI bus.
  • Page 46: I/O Mapping

    I/O addresses 170h-177h, 376h and interrupt IRQ15. No memory addresses are used. CompactFlash Carrier Intel provides an optional IDE CompactFlash Carrier (ZT 96080) that can be mounted in the hard drive location on the ZT 5504. This carrier accommodates multiple types of CompactFlash cards, which appear to the system as a hard drive, and are automatically supported by most operating systems.
  • Page 47: Watchdog Timer

    7. Watchdog Timer This chapter explains the operation of the ZT 5504's watchdog timer. It provides an overview of watchdog operation and features, as well as sample code to help you learn how the watchdog timer works with applications. Watchdog Timer Overview The primary function of the watchdog timer is to monitor the ZT 5504's operation and take corrective action if the software fails to function as programmed.
  • Page 48: Power Up Initialization

    7. Watchdog Timer Power Up Initialization The watchdog timer's logic is initialized at power up. This ensures that the STAGE1 MONITOR, STAGE2 MONITOR, STAGE1 ENABLE, and STAGE2 ENABLE status and control bits power up to unasserted states (0). This allows an application to determine if the reset was caused by a watchdog timeout or a power up.
  • Page 49: Setting The Terminal Count

    7. Watchdog Timer Setting the Terminal Count The terminal count determines how long the watchdog waits for a strobe before resetting the hardware. C code for setting the terminal count might look like the following: #define WD_CSR_IO_ADDRESS 0x79 // IO address of the watchdog #define WD_T_COUNT_MASK 0x07 // Bit mask for terminal count bits.
  • Page 50: Chaining The Isrs

    7. Watchdog Timer Chaining the ISRs Save the original NMI ISR vector so that it can be invoked from the new watchdog NMI ISR. Alter the interrupt vector table so that the NMI ISR vector is overwritten with a vector to the watchdog ISR.
  • Page 51: Nmi Handler

    7. Watchdog Timer NMI Handler Because an NMI may originate from a source such as a RAM Error Correction Code (ECC) error, the NMI handler cannot assume that an NMI occurred due to a watchdog timeout. Therefore, the NMI handler must check the watchdog status register before taking watchdog- related emergency action.
  • Page 52: Bios Recovery

    BIOS or update it if it becomes corrupted, use the BIOS Recovery Module FLASH.EXE utility available from Intel and discussed later in this chapter. The flash memory is write-protected through switch SW3-2. BIOS Recovery Socket Location Pin 1 BIOS Recovery Socket U38 Artisan Technology Group - Quality Instrumentation ...
  • Page 53: Bios Recovery Module

    To reprogram the BIOS on the ZT 5504, use the following syntax at a DOS prompt: FLASH /b BIOS.XXX where BIOS.XXX is the BIOS image for the ZT 5504. See the Intel NetStructure Embedded BIOS Manual for more information on the flash utility.
  • Page 54: Specifications

    A. Specifications This appendix describes the electrical, environmental, and mechanical specifications of the ZT 5504. It includes connector descriptions and pinouts, as well as illustrations of the board dimensions and connector locations. Electrical and Environmental The topics listed below provide tables and illustrations showing the following electrical and environmental specifications: •...
  • Page 55: Battery Backup Characteristics

    Used batteries must be disposed of according to the manufacturer's instructions. Return the board to Intel for battery service. Operating Temperature The ZT 5504's heatsink allows a maximum ambient air temperature of 50°C with 200 LFM (linear feet per minute) of airflow.
  • Page 56: Mechanical

    A. Specifications Mechanical This section includes the following mechanical specifications: • Dimensions and weight • Connector locations, descriptions, and pinouts Board Dimensions and Weight The ZT 5504 meets the CompactPCI Specification, PICMG 2.0, Version 2.1 for all mechanical parameters. In a CompactPCI enclosure with 0.8 inch spacing. Mechanical dimensions are shown in the "PCB Dimensions"...
  • Page 57: Connectors

    A. Specifications Connectors As shown in the "Connector Locations" figure, the ZT 5504 includes several connectors to interface to application-specific devices. A brief description of each connector is given in the "Connector Assignments" table below. A detailed description and pinout for each connector is given in the following topics.
  • Page 58: Backplane Connectors - Pin Locations

    A. Specifications Connector Locations ENETB ENETA COM1 USB1 USB0 J9 J8 J14 Primary IDE J13 PMC J16 PMC Backplane Connectors - Pin Locations Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 59: J1 (Compactpci Bus Connector)

    A. Specifications J1 (CompactPCI Bus Connector) J1 is a 110-pin, 2 mm x 2 mm, female 32-bit CompactPCI connector (AMP 352068-1). Rows 12-14 are used for connector keying. See the "J1 CompactPCI Bus Connector Pinout" table below for pin definitions. Refer to the "Backplane Connectors –...
  • Page 60: J2 (Compactpci Bus Connector)

    A. Specifications J2 (CompactPCI Bus Connector) J2 is a 110-pin 2 mm x 2 mm female 64-bit CompactPCI connector (AMP 352152-1). See the "J2 CompactPCI Bus Connector Pinout" table for pin definitions and the "Backplane Connectors - Pin Locations" illustration for pin placement. J2 CompactPCI Bus Connector Pinout Pin# SS_CLK6...
  • Page 61: J3 (Compactpci Connector)

    A. Specifications J3 (CompactPCI Connector) J3 is a 95-pin 2 mm x 2 mm female connector (AMP 352171-1). See the "J3 Connector Pinout" table below for pin definitions and the "Backplane Connectors - Pin Locations" illustration for pin placement. J3 Connector Pinout Pin# RP_TXA+ RP_TXA-...
  • Page 62: J5 (Rear Panel I/O Compactpci Connector)

    A. Specifications J5 (Rear Panel I/O CompactPCI Connector) J5 is a 110-pin 2 mm x 2 mm female connector (AMP 352152-1) providing rear-panel user I/O. See the "J5 Rear Panel I/O Connector Pinout" table below for pin definitions and the "Backplane Connectors - Pin Locations"...
  • Page 63: Ja4 And J17 (Ethernet A And B Connectors)

    A. Specifications JA4 and J17 (Ethernet A and B Connectors) JA4 (Ethernet A) and J17 (Ethernet B) are 8-pin RJ-45 connectors providing both 10 Mbit (10BASE-T) and 100 Mbit (100BASE-TX) protocols. Two LEDs are located inside each RJ-45 connector: • Yellow indicates activity •...
  • Page 64: J8 And J9 (Universal Serial Bus 0 And 1 Connectors)

    A. Specifications J8 and J9 (Universal Serial Bus 0 and 1 Connectors) J8 (Port0) and J9 (Port1) are Universal Serial Bus (USB) Interface connectors (AMP 440260- 1). See the "J8 and J9 Universal Serial Bus 0 and 1 Connector Pinout" table below for pin definitions.
  • Page 65: J13 And J16 (Pci Mezzanine Connectors)

    A. Specifications J13 and J16 (PCI Mezzanine Connectors) J13 and J16 are 64-pin, 1.00mm, dual row, vertical stacking receptacles providing a PCI local bus interface to optional PMC cards. These connectors provide a complete 32-bit PCI interface. See the following "J13 PCI Mezzanine Connector Pinout"...
  • Page 66: J16 Pci Mezzanine Connector Pinout

    A. Specifications J16 PCI Mezzanine Connector Pinout Signal Signal +12V VCC3 PMC2-BUSMODE2 B0_PCIRST- PMC2-BUSMODE3 VCC3 PMC2-BUSMODE4 B0_PAD30 B0_PAD29 B0_PAD26 B0_PAD24 VCC3 B0_PAD23 PMC2_IDSEL VCC3 B0_PAD20 B0_PAD18 BO PAD16 B0_CBE-2 B0_TRDY- VCC3 B0_STOP- B0_PERR- VCC3 B0_SERR- B0_CBE-1 B0_PAD14 B0_PAD13 B0_PAD10 B0_PAD8 VCC3 B0_PAD7 VCC3...
  • Page 67: J14 (Ide Connector)

    A. Specifications J14 (IDE Connector) J14 is a 44-pin, male, 2mm (.079") header (Samtec EHT-122-01-S-D), providing a primary channel IDE interface. See the "J14 IDE Connector Pinout" table below for pin definitions. J14 IDE Connector Pinout Pin# Signal Pin# Signal RST- DDP7 DDP8...
  • Page 68: Thermal Considerations

    CAUTION: External airflow must be provided at all times during operation to avoid damaging the CPU. Intel strongly recommends the use of a fan tray below the card rack to supply the external airflow. The "Thermal Requirements" table below shows the relationship between ambient air temperature, board temperature, and processor core temperature.
  • Page 69: Temperature Monitoring

    Temperature Monitoring Because reliable long-term operation of the ZT 5504 depends on maintaining proper temperature, Intel strongly recommends verifying the operating temperature of the processor module and processor core in the final system configuration. The Pentium III processor incorporates an on-die thermal diode that can be used to monitor the processor's die temperature.
  • Page 70: System Registers

    C. System Registers The ZT 5504 provides several system registers to control and monitor a variety of functions. Normally, only the system BIOS uses these registers, but they are documented here for application use as needed. Take care when modifying the contents of these registers, as the system BIOS may be relying on the state of the bits under their control.
  • Page 71: Flash Control (78H)

    C. System Registers Flash Control (78h) I/O Address: Default Value: 0x00 Size: 8 bits Attribute: Note: This register is reset to 00h on init or reset. The BIOS resides in page 000. Description Default Flash Write Protection Controls Write Enable to flash: 0 = Write protects flash.
  • Page 72: Watchdog (79H)

    C. System Registers Watchdog (79h) I/O Address: Default Value: 0x00 Attribute: Description Stage 2 Monitor (Reset Monitor) Monitors the second stage (Reset) timer status. Read Value: 0 = Watchdog has not timed out since power up or since this bit was last set to 0. 1 = Watchdog reset timeout occurred since power up or since bit was last set to 0.
  • Page 73 C. System Registers Watchdog (79h), continued Description Stage 2 Enable Enables second stage (Reset) activation on timeout. Read Value: 0 = Reset activation on timeout disabled. 1 = Reset activation on timeout enabled. Write Value: 0 = Reset operation of the watchdog is not enabled. When the watchdog times out, Stage 2 Monitor bit is not set to 1 and the Reset output is not asserted.
  • Page 74 C. System Registers Watchdog (79h), continued Description NMI or INIT Selects between generating an NMI or a CPU INIT. Read Value: 0 = NMI 1 = INIT This bit is set to 0 at reset. Write Value: 0 = NMI is generated when the watchdog times out. 1 = INIT is generated when the watchdog times out.
  • Page 75: J1 Ipmb Control (7Bh)

    C. System Registers J1 IPMB Control (7Bh) I/O Address: Default Value: 0x00 Attribute: Description RESERVED J1 IPMB Enable Connect/disconnect IPMB signals to the ZT 5504's J1 connector. Read Value: 0 = Disconnect. 1 = BMC IPMB is connected to J1. Write Value: 0 = Disconnect.
  • Page 76: Event Monitors (E1H)

    C. System Registers Event Monitors (E1h) I/O Address: Default Value: 0x00 Size: 8 bits Attribute: Description RESERVED ENUM- This bit displays the value of ENUM- from backplane J1-C25. A logical 0 means that ENUM- is not asserted on the backplane. A logical 1 means that ENUM- is asserted on the backplane.
  • Page 77: Geographic Addressing (E4H)

    This bit reads the status of switch SW4-4. A logical 0 means that SW4-4 is open and console redirection is not enabled. A logical 1 means SW4-4 is closed and console redirection is enabled. Refer to the "Console Redirection" chapter in the Intel NetStructure Embedded BIOS Manual before attempting to use this feature.
  • Page 78: Control Bits (E5H)

    C. System Registers Geographic Addressing (E4h), continued Geographic Addressing CompactPCI defines several signal additions to the PCI specification. One of these is GA[4..0], used for geographic addressing on the backplane. Geographic addressing uniquely differentiates each board based upon the physical slot into which it was inserted.
  • Page 79: Datasheet Reference

    Ethernet LAN Controller. The datasheet is available from Intel's Website at: http://developer.intel.com/design/network/index.htm Intel 440GX AGPset For more information on the following ZT 5504 functions, refer to the Intel 440GX AGPset: 82443GX Host Bridge/Controller datasheet. • USB • Counter/Timers •...
  • Page 80: Mobile Pentium Iii Processor - M In Bga2 Package

    Mobile Pentium III Processor - M in BGA2 Package For more information about the Intel Mobile Pentium III Processor - M in BGA2 Package, see the Mobile Intel Pentium III Processor - M in BGA2 and Micro-PGA2 Packages datasheet. This document is available online at: http://developer.intel.com/design/mobile/datashts/245302.htm...
  • Page 81: Agency Approvals

    E. Agency Approvals CE Certification The ZT 5504 meets the intent of Directive 89/336/EEC for Electromagnetic Compatibility and Low-Voltage Directive 73/23/EEC for Product Safety. The ZT 5504 has been designed for NEBS/ETSI compliance. Safety UL/cUL 60950 Safety for Information Technology Equipment (UL File # E179737) EN/IEC 60950 Safety for Information Technology Equipment CB Report Scheme...
  • Page 82 2. This device must accept any interference received, including interference that may cause undesired operation. CAUTION: If you make any modification to the equipment not expressly approved by Intel, you could void your authority to operate the equipment. Industry Canada (Canada) Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils...
  • Page 83 This appendix offers technical and sales assistance information for this product, and information on returning an Intel NetStructure product for service. Technical Support and Return for Service Assistance For all product returns and support issues, please contact your Intel product distributor or Intel Sales Representative for specific information Sales Assistance If you have a sales question, please contact your local Intel NetStructure Sales Representative or the Regional Sales Office for your area.
  • Page 84 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...