Mallinckrodt NELLCOR NPB-4000 Service Manual page 176

Section 14: Main Color Board Digital Theory of Operation
14.17.21.5 FE_CLK_EN BIT
14.17.21.6 PROG_EN BIT
14.17.21.7 ADCS_RESET BIT
14.17.22 STXCLK and ADCS/ CIRCUITS
14-36
Bit 5 is the FE_CLK_EN which stands for the front end clock enable bit. This
bit enables the 200 kHz signal to the front end power supply transformer. The
software has control over the front end power supply via this bit. The major
reason for having this bit is to reset the front end by turning the power OFF, then
ON again via this bit.
Bit 6 is the program enable bit for reprogramming or storing data in the
executable FLASH. This bit when high enables the +3.3 volts DC onto the
programming bit of the FLASH. This allows data to be written into the FLASH
by writing to the FLASH.
This bit when high resets the A/D converter and clears the STYXCLK signal. It
holds the A/D converter in reset state until this bit is set low. This bit exits the
FPGA via pin 162.
The A/D converter has a synchronous serial interface (SSIO) to the 386EX. The
3 signals are transmit data, receive data, and clock. When the SSIO port in the
386EX is programmed and activated, it operates in an unusual manner. If new
data is not ready after a transmission, the serial unit will transmit the same data
over again. The solution is to generate the synchronous serial clock in the FPGA
rather than the 386EX SSIO unit. The TIMER0' S output is routed to the FPGA
on pin 95 and enables a 25 kHz clock which goes out on pin 134. This is the
master synchronous serial clock and is routed to the A/D converter and the
386EX SSIO unit. The 386EX SSIO unit is programmed as a slave for the serial
clock and thus when it receives the serial clock from the FPGA it starts enabling
data onto the transmit line, and receives data on the receive line. The A/D
converter receives 16 clocks and then asserts its EOC signal which comes in on
pin 43. This turns off the serial clock and it doesn' t turn on again until the next
tick from the timer. (The serial clock can also be turned off by setting the
ADCS_RESET bit in the CONTROL Register of the FPGA.) This same timer
tick is routed to the 386EX DMA unit and a new piece of data is transferred to
the SSIO unit in a waiting buffer. After the present data is transmitted, the new
data is loaded into the transmit register and is ready for transmission on the next
timer tick. This solves the problem of the SSIO unit retransmitting data.