Cpu Connections - Mallinckrodt NELLCOR NPB-4000 Service Manual

13.7 CPU CONNECTIONS

13.7.1 Port 1 Signals
13.7.2 Port 2 Bits
Section 13: Microprocessor Computer and Control –Theory of Operation
The processor in this system is a 386EX. The 386EX contains a 386SX core and
integrated peripherals. It operates from a 40-MHz oscillator, and includes the
following on-board peripherals:
DMA Controller Unit
Bus Interface Unit
Chip-select Unit
Clock and Power Management Unit
DRAM Refresh Control Unit
Watch Dog Timer Unit
2 Asynchronous Serial I/O Units
Synchronous Serial I/O Unit
Timer Unit with three 16-bit Counter/Timers
Interrupt Control Unit
Three 8-Bit Digital I/O Ports
The connections are as follows:
Address bus connects to the LCD controller, RTC address/data mux,
DRAM address mux, and the boot and trend flashes. Six address lines
go to the FPGA.
The data bus connects to the data bus buffers, which in turn connect to
the DRAM, RTC, DUART, boot flash, trend flash, LCD controller, and
the FPGA.
The address and data control signals are distributed to the FPGA,
DRAM, RTC, LCD controller, boot and trend flashes, and DUART.
RESET comes from the FPGA.
CLK2 is a 40 MHz signal from the onboard oscillator.
Port 1 is connected to the following signals:
1.1 NIBP analog power on/off - out
1.2 NIBP 3-way valve on/off - out
1.3 NIBP neonatal measurement - out - not used
1.4 LCD contrast up - out
1.5 LCD contrast down - out
1.6 AC mains input status bit - in
1.7 DC input status bit - in
Port 2 bits used are as follows:
2.7 Speaker volume up/down select - out
13-9