Mallinckrodt NELLCOR NPB-4000 Service Manual page 158

Section 14: Main Color Board Digital Theory of Operation
14.13.1 CS5# NIBP PUMP PWM 8 BITS
14.13.2 CS5# + 4 SPEAKER HIGH, CS5# + 6 SPEAKER LOW VALUE
14.13.3 CS5# + 8 CONTROL REGISTER
14-18
The NIBP pump pulse width modulated (PUMP_PWM) signal is generated in
the FPGA via an 8 bit register which is clocked at 313 kHz. An 8 bit value is
loaded into this register and then the PUMP_PWM_GO bit (bit 0) in the
CONTROL REG. is set true and the pump PWM signal begins. The 8 bit
register starts counting down and the signal output is low until the counter
underflows, at which time it is reloaded with the programmed value. It now
counts up, and the signal output goes high until the counter overflows. It is then
reloaded and counts down, etc. The PUMP_PWM signal is generated this way
until it is shut off by resetting the PUMP_PWM_GO bit in the CONTROL REG.
The NIBP valve pulse width modulated (NIBPCNTLVLV) signal is generated in
the FPGA via this same 8 bit register which is clocked at 313 kHz. An 8 bit
value is loaded into this register and then the VALVE_PWM_GO bit (bit 1) in
the CONTROL REG. is set true and the valve PWM signal begins. The 8 bit
register starts counting down and the signal output is low until the counter
underflows, at which time it is reloaded with the programmed value. It now
counts up, and the signal output goes high until the counter overflows. It is then
reloaded and counts down, etc. The NIBPCNTLVLV signal is generated this
way until it is shut off by resetting the VALVE_PWM_GO bit in the CONTROL
REG.
The same register is used for both PWMs because they are mutually exclusive
and software uses only one at a time.
The speaker tone frequency is generated using two 8 bit registers, one which is
the value for the high portion of the frequency and one value for the low value
for the frequency. The frequency range is 200 Hz to 1000 Hz. The 16 bit
counter has a count frequency selectable of 78 kHz or 313 kHz. This selection is
programmed in the CONTROL REG. using the CLK_FREQ_SEL (bit 2). A 0
selects 156 kHz and a 1 selects 78 kHz. Once the values are loaded and the
frequency clock is selected the FREQ_GO bit (bit 3) is set to begin the tone
frequency. Software has complete control over the duty cycle of this tone by
programming the high and low values and being able to select the clock
frequency for the counter. The TONE_OUT signal is low until the low counter
overflows and sets the TONE_OUT flip flop high. Now the high counter is
enabled and the TONE_OUT signal stays high until the high counter overflows,
at which time it goes low and the low counter begins counting. This cycle
continues until the FREQ_GO bit is reset to 0.
This register has 8 programmable bits as follows:
BIT 0: PUMP_PWM_GO
BIT 1: VALVE_PWM_GO
BIT 2: CLK_FREQ_SEL
BIT 3: FREQ_GO
BIT 4: BCK_LITE_ON
BIT 5: FRONT END CLOCK ENABLE
BIT 6: PROGRAM FLASH ENABLE
BIT 7: ADCS RESET