Mallinckrodt NELLCOR NPB-4000 Service Manual page 173

14.17.16 FREQUENCY GENERATOR
14.17.17 LCD CONTROL
The master clock in, generates 2 internal signals, CLK_PH1 and CLK_PH2, both
of which are 20 MHz clocks 180 degrees out of phase with each other. The
CLK_PH1 is divided down into 10 MHz, 5 MHz, 2.5 MHz, 1.25 MHz, 525 kHz,
313 kHz, 156 kHz, and 78 kHz. The 10 MHz is output on pin 139 and goes to
the DUART controller as its master clock. 313 kHz is used by the NIBP PWM
circuits. The 156 kHz and 78 kHz are used by the speaker frequency generating
circuit.
The LCD CONTROL circuit generates the control signals for the SED1354, they
are RD_WR/, RD/, WR0/, WR1/, and CS/.
The RD/ is generated by anding BLEB/ with RDB/. The output signal is called
LCD_LRD/. This signal comes from pin 59 of the FPGA and goes to pin 7 of
the 1354.
The RD_WR/ is generated by anding BHEB/ with RD/. The output signal is
called LCD_URD/. This signal comes from pin 60 of the FPGA and goes to pin
10 of the 1354.
The WR0/ is generated by an AND gate and a flip flop. The AND gate is
"anding" BLEB/ with WRB/. The flip flop is used to delay the WR0/. The
reason for the delay is to ensure that data out of the 386 is valid and to meet the
maximum delay from WR0/ low to data valid of the 1354. The flip flop will
become cleared when ADS/ goes low for the start of the next cycle. The output
signal is called LCD_LWR/. This signal comes from pin 56 of the FPGA and
goes to pin 8 of the 1354.
The WR1/ is generated by an AND gate and a flip flop. The AND gate is
"anding" BHEB/ with WRB/. The flip flop is used to delay the WR1/. The
reason for the delay is to ensure that data out of the 386 is valid and to meet the
maximum delay from WR0/ low to data valid of the 1354. The flip flop will
become cleared when ADS/ goes low for the start of the next cycle. The output
signal is called LCD_UWR/. This signal comes from pin 58 of the FPGA and
goes to pin 9 of the 1354.
CS/ is essentially generated by "or' ing" LCD_CNTL_SEL/ with
LCD_MEM_SEL/. The First flip flop will become set when ADS/ and
PHI1_FPGA are both low to indicate the start of a cycle The Second flip flop
will get set when LCD_CNTL_SEL/ or LCD_MEM_SEL/ is low and the First
flip flop is set. The Third flip flop will get set 25 ns after the Second. The
reason for the third flip flop is to meet the minimum timing from WE0/ or WE1/
low to CS/ low of the 1354. The flip flops will stay latched until
LCD_CNTL_SEL and LCD_MEM_SEL/ are both high or if ADS/ goes low.
The output signal is called LCD_CS/. It comes from the FPGA pin 53 and goes
to pin 4 of the 1354.
Section 14: Main Color Board Digital Theory of Operation
14-33