Mallinckrodt NELLCOR NPB-4000 Service Manual page 172

Section 14: Main Color Board Digital Theory of Operation
14.17.13 RTC/DUART STATE MACHINE
14.17.14 RTC CONTROL
14.17.15 DUART CONTROL
14-32
Interfacing to the DUART and RTC requires slowing down the signals. A 20
state machine is implemented to interface to these circuits. The state machine
always starts up when ADSB/ is low and CLK_PH1 is high. The RTC1AFF is
set high on the rising edge of the master clock, CLK2_40MHZ. If the RTC or
DUART is not selected, the state machine is reset on the next CLK2_40MHZ.
The first 2 flip flops of the state machine are clocked on the CLK2_40MHZ
rising edge, while the remaining flops are clocked on the rising edge of
CLK_PH1, which occurs at the beginning of each state. The time between the
rising edges of this clock is 50 ns. The total time for the state machine is 1000
ns (1 us). This is required for the RTC, but the DUART only requires 4 states,
200 ns. The software programs the CS4 (DUART) for 2 wait state and the RTC
for 18 wait states.
The RTC control signals consist of READ_RTC, WRITE_RTC, RTC_ADREN/,
and RTC_ALE. These are all generated from the state machine cycles. The
RTC has a multiplexed address/data bus, and, therefore, requires that the bi-
directional data bus be tri-stated while the address is enabled to the RTC. The
ENDTABFR signal is disabled high if the RTC is selected. It is jammed high by
the ENDTARTCAND gate which ands RTC_SEL/ low and RTCS8 low.
ENDTABFR goes low at the start of state 9 by anding RTCS9 low and RTCS8
high. During the time ENDTABFR is high, the address is enabled by
RTC_ADREN/, which is generated when RTCS2 is high and while RTCS8 is
low. At this same time RTC_ALE is generated between states 1 and 5, latching
the address into the RTC. When state 9 is reached, either a read or write
happens, depending on the state of the WR/ and RD/ signals. The READ_RTC
is generated between the states 9 and 20, while WRITE_RTC is generated
between the states of 9 and 19. The READ_RTC generates FDRRD/ on pin 46.
The WRITE_RTC generates WRITE/ on pin 2.
In review, the RTC control has to enable the address to the RTC and generate the
RTC_ALE signal to latch the address. Next, the data buffer must be enabled in
the proper direction and the read or write signals generated.
The DUART has 2 UART channels within one chip, and the chip select (CS4) is
used for both. The base address is used to program UART channel 0, and the
base address + 80 hex is used to program UART channel 1. This decoding is
done under the DUART control section and the 2 chip selects (DURT0_CS and
DURT1_CS). The software programs 2 wait states for the DUART. The
READ_DUART signal is generated from the state machine states 1 to 3, shutting
off in state 4. This gives a 150 ns read pulse. The write pulse is generated from
states 1 to2, shutting off in state 3, generating a 100 ns write pulse. This gives a
50 ns hold time on the data to the DUART.