Mallinckrodt NELLCOR NPB-4000 Service Manual page 149

Section 14: Main Color Board Digital Theory of Operation
14.6.1.1 DRAM TIMING
Figure 14-4: DRAM Timing
The DRAM requires 104 ns total time, read/write and precharge for each cycle.
There is 1 wait state for each DRAM access and a total of 3 T states which is
150 ns. Since the DRAM minimum access time is 104 ns, we have 46 ns of
margin. We are using the Hitachi HM51W18165LTT or equivalent which has a
RAS* time of 60 ns, a precharge time of 40 ns, a CAS* time of 10 ns, and a
WE* time of 10 ns. The BLE* and BLH* signals are used to select byte oriented
reads and writes. There are 2 CAS* lines, which are used to implement the byte
writes.
The RAS# and CAS# requirements are shown below.
Figure 14-5: RAS# and CAS# Timing
14-9