Mallinckrodt NELLCOR NPB-4000 Service Manual page 151

14.7.2 FLASH FPGA CONTROL CIRCUIT
In the FPGA control logic, the executable flash chip select is anded with the
trend flash chip select such that CS2* must be high, inactive, when addressing
the executable flash. This allows the address overlap for the trend flash. The
executable flash chip enable FLSH1CE# is generated in the FPGA and then goes
to the executable flash. The trend flash is connected directly to CS2# because it
has priority over the executable if an overlapping addressing scheme is used. The
write pulse width is generated via a state machine to give the proper pulse width
The FPGA decodes the boot flash and trend flash select signals and generates the
boot flash (FLSH1CE#) signal whenever the trend flash is not being accessed.
Since the trend flash address space may overlap the boot flash space, the trend
flash has priority.
The flash outputs are enabled for a read cycle. During a write cycle, the data bus
inputs data to the flash.
Section 14: Main Color Board Digital Theory of Operation
Figure 14-6: Flash Read Timing
Figure 14-7: Flash Write Timing
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