Mallinckrodt NELLCOR NPB-4000 Service Manual page 170

Section 14: Main Color Board Digital Theory of Operation
14.17.4 CONTROL REGISTER DECODE
14.17.5 PUSH BUTTON INTERRUPT
14.17.6 WATCH DOG TIMER ENABLE
14.17.7 REGISTER 30E
14.17.8 FLASH CHIP ENABLE
14-30
The CONTROL REGISTER decoder is a 1 of 8 decoder which decodes the
register addresses for the 8 control registers in the FPGA. The decoder generates
a high going pulse coincident with WRB/ on 1 of the 8 output signal lines. The
register addresses are as follows:
1. LOAD NIBP PUMP PWM
2. LOAD CONTRAST PWM
3. LOAD SPEAKER HIGH
4. LOAD SPEAKER LOW
5. LOAD CONTROL REG
6. RESET KNOB INTERRUPT
7. ENABLE WATCH DOG
TIMER
8. LOAD CONTROL REG 2
The function of each of these registers is explained later.
When a membrane switch is pressed, a low true signal occurs. All of the
membrane switches are or' ed together to generate the PBINTPD signal which is
read via the status register. This signal also comes out on pin 81 of the FPGA
for testing purposes only. It does not go the 386EX interrupt inputs. The
software polls the status register at a known rate and checks to see if this bit is
set.
The WDT output from the 386EX is anded with a 50 kHz signal which is derived
from the 100 kHz output of timer 2 of the 386EX. When powering up the WDT
is not in the correct mode of operation until the software programs it. Therefore,
to prevent the power supply from shutting down prematurely, the WDTENFF
must be set high after the WDT has been programmed. Writing to address 30C
automatically sets this bit high and enables the WDT function.
This register has 2 bits, NSCALL (nurse call) and PTRRST (printer reset). Each
of these bits can be set high or low by programming the bit 6 for the PTRRST
signal and bit 7 for the NSCALL signal. The NSCALL signal goes out on pin
123 and PTRRST goes out on pin 151.
The EXECUTABLE FLASH chip is assigned to UCS (upper chip select) and the
TREND FLASH is assigned to CS2. Software requested that they be able to
map the TREND FLASH in the EXECUTABLE FLASH address space. To
accomplish this the TREND FLASH selection has priority over the
EXECUTABLE FLASH. Thus, the EXECUTABLE FLASH chip select must be
conditioned with the TREND FLASH chip select. This is done by anding
BOOTFLSHSEL/ low with TRND_FLSH_SEL/ high and M_IOB/ high. The
FLSH1CE/ low gets generated whenever the BOOT FLASH is being addressed
and the TREND FLASH is not being addressed.
ADDRESS 300 HEX
ADDRESS 302 HEX, NOT USED
ADDRESS 304 HEX
ADDRESS 306 HEX
ADDRESS 308 HEX
ADDRESS 30A HEX
ADDRESS 30C HEX