Lna 386Ex Connections; Cpu Timing Signals - Mallinckrodt NELLCOR NPB-4000 Service Manual

14.3.8 ASYNCHRONOUS SERIAL PORT
14.3.9 WATCH DOG TIMER UNIT (WDT)

14.4 LNA 386EX CONNECTIONS

14.5 CPU TIMING SIGNALS

time a new conversion is initiated the previous conversion' s data is transferred to
the 386EX via the SSIORX data line.
There are 2 asynchronous UART ports on the 386EX, but only one is used. It is
connected to the opto-isolators that connect to the SPO2 unit.
TXD0: asynchronous transmit signal
RXD0: asynchronous receive signal
The watchdog timer unit within the 386EX has one output which goes to the
FPGA.
Figure 14-2: LNA 386EX CONNECTIONS
The 386EX runs from a 40mhz crystal oscillator and the main timing is derived
from this clock. It is called CLK_40MHZ. Inside the CPU CLK_40MHZ is
divided by 2, generating two new clocks, PH1 and PH2. Each T state is made up
of one PH1 and one PH2 clock. There are a minimum of 2 T states per cycle.
Each wait state is one T state long (50 ns). Therefore, adding wait states is like
adds 50 ns on for each wait state.
Section 14: Main Color Board Digital Theory of Operation
14-7