Switch Control; Miscellaneous Control - Cs5 - Mallinckrodt NELLCOR NPB-4000 Service Manual

Section 13: Microprocessor Computer and Control –Theory of Operation

13.14 SWITCH CONTROL

13.15 MISCELLANEOUS CONTROL - CS5#

13.15.1 CS5# NIBP Pump PWM 8 Bits
13-20
The knob has two channels: channel A and channel B. When clockwise rotation
occurs, channel A leads channel B and when counterclockwise rotation occurs,
channel B leads channel A. The software monitors the knob flip flop, and when
it is set true, the knob has turned. The direction is read by the other bits in the
status register, and the software determines the knob direction. The KNOBINT
flip flop is reset by the software when a write to CS5# + A occurs. The knob
direction is determined by the software by reading CS5# + A, bits 4 and 5.
The circuit that drives the knob is a 3.3 volts circuit, with appropriate resistor
values to allow the same current at 3.3 volts through the optocouplers as would
have occurred at 5 volts.
There are five switches and one knob push-button switch. All of these switches
go to the FPGA control circuit except for the On/Standby switch, which goes
directly to the power supply control circuit. Each of the switch circuits has a
debounce resistor and capacitor associated with it and then goes to the FPGA.
The signals ALRMSIL, NIBPPB, AUDTONVOL, LCDCONTRST, and
KNOBPB go to the FPGA where they are OR' d together and exit as PBINT.
This is read by the software in the status register. The software debounces and
detects the length of time the switch is depressed. The software determines
which switch was depressed by reading CS5# + A, bits 4 through 7.
The NIBP PUMP PWM, NIBP VALVE PWM, SPEAKER FREQUENCY
DUTY CYCLE, and a miscellaneous control register are all assigned to the I/O
space programmed to CS5#. The addressing scheme is as follows:
CS5# NIBP PUMP PWM
CS5# + 2 Not used
CS5# + 4 SPEAKER HIGH VALUE
CS5# + 6 SPEAKER LOW VALUE
CS5# + 8 CONTROL REG
CS5# + A WRITE RESETS KNOB INT/READ PUSH SWITCHS and
the KNOB ROTATION DIRECTION bits
CS5# + C WRITE WDTEN (WATCHDOG TIMER ENABLE)/READ
PUSH SWITCH SWITCHES AND THE KNOB PUSH
BUTTON
CS5# + E WRITE NSCALL (BIT 7) and/or PTRRST (BIT 6)/RAD
NSCALL and PTRRST
The NIBP pump pulse width modulated (PUMP_PWM) signal is generated in
the FPGA via an eight-bit register which is clocked at 313 kHz. An eight-bit
value is loaded into this register, and then the PUMP_PWM_GO bit (bit 0) in the
CONTROL REG. is set true, and the pump PWM signal begins. The eight-bit
register starts counting down, and the signal output is low until the counter
underflows, at which time it is reloaded with the programmed value. It now
counts up, and the signal output goes high until the counter overflows. It is then
reloaded and counts down. The PUMP_PWM signal is generated this way until
it is shut off by resetting the PUMP_PWM_GO bit in the control reg.
8 bits
8 bits
8 bits
8 bits