Mallinckrodt NELLCOR NPB-4000 Service Manual page 135

13.15.2 CS5# + 4 Speaker High, CS5# + 6 Speaker Low Value
13.15.3 CS5# + 8 Control Register
Section 13: Microprocessor Computer and Control –Theory of Operation
The NIBP valve pulse width modulated (NIBPCNTLVLV) signal is generated in
the FPGA via this same eight-bit register, which is clocked at 313 kHz. An
eight-bit value is loaded into this register, and then the VALVE_PWM_GO bit
(bit 1) in the control reg. is set true, and the valve PWM signal begins. The
eight-bit register starts counting down, and the signal output is low until the
counter underflows, at which time it is reloaded with the programmed value . It
now counts up, and the signal output goes high until the counter overflows . It is
then reloaded and counts down. The NIBPCNTLVLV signal is generated this
way until it is shut off by resetting the VALVE_PWM_GO bit in the control reg.
The speaker tone frequency is generated using two eight-bit registers, one which
is the value for the high portion of the frequency and one value for the low
portion for the frequency. The frequency range is 200 Hz to 1000 Hz. The
16-bit counter has a selectable count frequency of 78 kHz or 313 kHz. This
selection is programmed in the control reg. using the CLK_FREQ_SEL (bit 2).
Signal A 0 selects 313 kHz and a 1 selects 78 kHz. Once the values are loaded,
and the frequency clock is selected, the FREQ_GO bit (bit three) is set to begin
the tone frequency. Software has complete control over the duty cycle of this
tone by programming the high and low values and being able to select the clock
frequency for the counter. The TONE_OUT signal is low until the low counter
overflows and sets the TONE_OUT flip flop high. Now the high counter is
enabled, and the TONE_OUT signal stays high until the high counter overflows,
at which time it goes low and the low counter begins counting . This cycle
continues until the FREQ_GO bit is reset to zero.
This register has eight programmable bits as follows:
BIT 0 PUMP_PWM_GO
BIT 1 VALVE_PWM_GO
BIT 2 CLK_FREQ_SEL
BIT 3 FREQ_GO
BIT 4 BCK_LITE_ON
BIT 5 FRONT END CLOCK ENABLE
BIT 6 PORGQM FLASH ENABLE
BIT 7 ADCS RESET
Bits 0 through 3 were defined in the above paragraphs and need no further
explanation here. Bit 4, BCK_LITE_ON is a bit that turns on the LCD backlight
when set to a 1. When powered on, this bit is 0 and the backlight is off. To turn
on the backlight this bit must be set to a 1.
Bit 5 enables the clock going to the Front End transformer, that generates the
isolated Front End voltages. If the Front End should ever go into a baseline
condition, it is reset by stopping the clock to the transformer, and the Front End
voltage will go to zero. Turning this bit back on powers the Front End up and,
essentially, acts as a reset.
Bit 6 enables programming of the boot flash. This would be used if a new
executable program were downloaded via the RS-232 channel and stored in the
executable flash.
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