Mallinckrodt NELLCOR NPB-4000 Service Manual page 169

14.17.3.2 DRAMOE/ CONTROL CIRCUIT
14.17.3.3 CASADREN SIGNAL
14.17.3.4 WRITE SIGNAL
14.17.3.5 ENDTABFR SIGNAL
The DRAMOE/ signal enables the output drivers in the DRAM which is
activated on a read of the DRAM memory. DRAMOE/ is generated from RAS1/,
BLEORBHE, WRB/, and LCD_MEM_SEL/. The RAS1/ must be low,
indicating that a DRAM access is beginning. The BLEORBHE is high (true)
and indicates that a valid read is occurring. The WRB/ must be high indicating
that a write is not taking place, and LCD_MEM_SEL/ is high indicating that the
memory location is mapped to DRAM and not LCD memory.
The CASADREN signal is a signal which enables the row address and column
address to the DRAM when RAS/ and CAS/ are generated. This signal is high
and enables the row address when RAS/ goes low and remains high until RAS1/
goes low at which time CASADREN goes low, enabling the column address.
This occurs 25 ns before LCAS/ or UCAS/ goes low. It is connected to the
RAS1/ signal and stays low for 75 ns.
The WRITE/ signal is generated for writing to DRAM, FLASH, RTC, and the
DUART. Writing to the DRAM occurs when RAS1/ is true, WRB/ is true,
LCD_MEM_SEL/ is false, and D_CB is high, indicating a data operation. As a
note, a WRITE/ must be generated in glue logic because various memory and
peripheral chips require a hold time when writing data to it. The 386EX turns
the WR/ signal off at the end of the last T2 state of a cycle. When this happens,
the data bus buffer is also turned off and the data lines go into a tri-state
condition. This can happen rather quickly, (less then 5 ns) and cannot guarantee
a decent hold time for the data being written.
The signal ENDTABFR is a low true signal and enables the data bus buffer on
the Mother Board (D5-18055) to transfer data to or from the 386EX. It powers
up in the high state and is set low when ADSB/ goes low, which signifies that a
new cycle is beginning. This is true for all transfers except if the RTC is
selected. If the RTC is selected then the signal doesn' t go low until state 9 of the
RTC state machine. This is ensured by jamming the D input with a high signal
generated by the anding of RTC_SEL low and the state machine having not
reached state 8. When ENDTABFR is low, it is set high again when the
READY/ signal goes low, signifying the end of a cycle. The RTC has a
multiplexed address/data bus and requires that the data bus buffer be tri-stated
when the address is enabled to the RTC chip.
Section 14: Main Color Board Digital Theory of Operation
14-29