Mallinckrodt NELLCOR NPB-4000 Service Manual page 124

Section 13: Microprocessor Computer and Control –Theory of Operation
13.7.3 Port 3 Bits
13.7.4 Chip Select Unit
13.7.5 Timer Unit
13.7.6 Interrupts
13-10
Port 3 bits used are as follows:
3.2 Defib key input - in
3.5 PSOFF - out
3.6 Defib sync pulse - out
3.7 NIBP PV enable - in
The chip select unit has 8 chip selects and are defined as follows:
CS0: LCD control register select - eight-bit I/O
CS1: LCD memory select - 16-bit memory
CS2: Trend flash select - eight-bit memory
CS3: RTC select - eight-bit I/O
CS4: Duart select - eight-bit I/O
CS5: Misc. control/status registers - NIBP control, switch status, and
speaker tone control - eight-bit I/O
CS6: DRAM select - 8/16-bit memory
UCS: Executable flash select - 16-bit memory
There are wait states associated with each of the CSU' s selects, and they are
defined as follows:
CS0: read/write - six wait states
CS1: read/write - six wait states
CS2: read/write - four wait states
CS3: read/wrote - 18 wait states
CS4: read/write - two wait states
CS5: read/write - no wait states
CS6: read/write - one wait state
UCS: read - two wait states/write - four wait states
The timer unit has three timers: two are used for output control, and one is used
to initiate DMA transfers to the A/D converter.
TIMEROUT0: Speaker volume adjust pulse
TIMEROUT1: A request for initiating an A/D conversion
TIMEROUT2: 100 kHz output to the FPGA for generating the 100 kHz
There are five interrupts used:
INT1: DUART channel 1 interrupt
INT2: DUART channel 2 interrupt
INT5: Early warning from the power supply
(Also connected to INT 7)
and 50 kHz signals for the power supply