Mallinckrodt NELLCOR NPB-4000 Service Manual page 165

Section 14: Main Color Board Digital Theory of Operation
the previous conversion is transferred to the 386EX. The SSIO unit works with
the both of the DMA units in the 386EX as well as the timer unit.
The functional operation of the DMA, SSIO, A/D Converter, and the front end is
as follows. Software sets up DMA CHANNEL 0 to transfer from DRAM a
buffer which contains 16 bit control words. The timer is set up to generate a
pulse every 1.25 ms (800 Hz rate). DMA CHANNEL 1 is set up to transfer data
from the SSIO receive buffer to a DRAM buffer. The SSIO unit is set up to
transmit and receive data when it receives a serial clock. Once set up all of the
above circuits work together with the FPGA serial clock circuit to initiate a
conversion and transfer the conversions into memory.
The timer output is routed to DMA CHANNEL 0 and the FPGA. The DMA unit
transfers a 16 bit control word from DRAM to the SSIO transmit buffer. At the
same time the FPGA starts synchronizing to the 25 kHz clock generated
internally in the FPGA. The FPGA circuit generates a serial clock which goes to
the SSIO clock input and the A/D converter clock input. The SSIO transmit unit
starts transmitting the 16 bit control word to the A/D and the front end. The A/D
converter receives and interprets the first 8 bits, and ignores the last 8 bits. The
front end ignores the first 8 bits and stores the last 8 bits. At the same time that
it is receiving the control word, the A/D transmits to the SSIO receive unit the
data from the previous conversion. Three things are happening at once. The
A/D starts a new conversion after receiving the control word, the A/D transmits
to the SSIO the previous conversion' s data, and the front end changes it' s
multiplexer to the new input channel. Since the A/D converter has its own
sample and hold, once the conversion begins, the input to the A/D can change
without affecting the conversion. Thus, the front end sets up for the next
conversion, the A/D starts a conversion, and the A/D also transmits the previous
conversion' s data. Once the DMA unit receives the new data word from the A/D
it transfers it to the DRAM memory.
There is a specific sampling scheme for converting the analog signals. The A/D
converter' s sampling sequence is programmed by software. The channel
selections for the A/D and the front end are contained in the control words
transmitted by the SSIO. Since the A/D is a pipelined converter, the A/D
channel address sent is for the next conversion, and the front end channel
address is for the second conversion. Thus, when a control word is sent, it
contains the A/D channel to convert, and the front end channel for the next
conversion. The data that gets transferred is for the previous channel. Sampling
occurs every 1.25 ms (800 Hz rate), and there is room for 20 samples in a cycle.
The samples are repeated every 500 ms.
14.16.1 TIMER/DMA/SSIO INTERFACE
The software sets up TIMER1 to generate an output at an 800 Hz rate (1.25 ms).
The timer is routed to DMA CHANNEL 0 which is programmed to transfer a 16
bit control word to the SSIO transmit holding buffer. The SSIO transmits this
word to the A/D and the front end. The A/D stores the first 8 bits and the front
end stores the last 8 bits. At the same time the A/D transfers to the SSIO receive
buffer the previous conversions data. When the SSIO receive buffer becomes
full, it starts DMA CHANNEL 1, which transfers the data word to memory from
the SSIO receive buffer. This process continues indefinitely.
14-25