Mallinckrodt NELLCOR NPB-4000 Service Manual page 125

13.7.7 Synchronous Serial Port
13.7.8 Asynchronous Serial Port
13.7.9 Watch Dog Timer Unit (WDT)
Section 13: Microprocessor Computer and Control –Theory of Operation
The synchronous serial port is connected to the A/D converter. The signals used
are as follows:
STXCLK:
SRXCLK:
SSIOTX:
SSIORX:
The STXCLK signal is generated in the FPGA circuit each time Timer 1 initiates
a pulse (1.25 millisecond intervals). There are 16 clock pulses generated by
enabling a 25 kHz signal to the STXCLK line. The A/D is programmed for
16-bit transfers, and when the A/D receives the 16
EOC signal that turns off the STXCLK signal. The A/D makes a conversion and
passes the data back the next time it receives the STXCLK signal. The
SRXCLK signal is connected to the STXCLK, and each time a new conversion
is initiated, the previous conversion' s data is transferred to the 386EX via the
SSIORX data line.
There are two asynchronous UART ports on the 386EX, but only one is used. It
is connected to the opto-isolators that connect to the SpO
TXD0: asynchronous transmit signal
RXD0: asynchronous receive signal
The remaining port is reserved for future use.
See Figure 13-6. The watchdog timer unit within the 386EX has one output
which goes to the FPGA.
Figure 13-6: Watch Dog Timer Block Diagram
synchronous transmit clock
synchronous receive clock
synchronous transmit data
synchronous receive data
th
clock, it will activate the
unit.
2
13-11