Cpu Connections - Mallinckrodt NELLCOR NPB-4000 Service Manual

14.3 CPU CONNECTIONS

14.3.1 PORT 1 SIGNALS
14.3.2 PORT 2 BITS
14.3.3 PORT 3 BITS
The CPU (U7) is a 386EX microcontroller, which contains a 386SX core and
various integrated peripherals. The 386EX operates from a 40 MHz oscillator
(X3) and has the following on board peripherals:
• DMA Controller Unit
• Bus Interface Unit
• Chip-select Unit
• Clock and Power Management Unit
• Dram Refresh Control Unit
• Watch Dog Timer Unit
• Asynchronous Serial I/O Units
• Synchronous Serial I/O Unit
• Timer Unit with 3 16 Bit Counter/Timers
• Interrupt Control Unit
• Bit Digital I/O Ports
The 386EX' s address bus connects to the LCD controller (U500), RTC
address/data mux (U3), DRAM address mux (U2, U6, U8), and the boot (U504)
and trend flash (U14). Six address lines go to the FPGA (U505). The 386EX' s
data bus connects to the data bus buffers, which in turn connect to the DRAM
(U501), RTC (U4), DUART (U24), boot flash, trend flash, LCD controller, and
the FPGA. The 386EX' s control signals are distributed to the FPGA, DRAM,
RTC, LCD controller, boot and trend flash, and DUART. Reset to the 386EX is
generated in the FPGA.
CLK_40MHZ is a 40 MHz signal from the on board oscillator.
Port 1 is connected to the following signals:
1.0 NU
1.1 NIBP analog power on/off - out
1.2 NIBP 3-way valve on/off - out
1.3 NIBP neonatal measurement - out
1.4 NU
1.5 NU
1.6 AC mains input status bit - in
1.7 DC input status bit - in
Port 2 uses one bit.
Speaker volume up/down select - out
Port 3 bits used are as follows:
3.2 Defib key input - in
3.5 PSOFF - out
3.6 Defib sync pulse - out
3.7 NIBP PV enable - in
Section 14: Main Color Board Digital Theory of Operation
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