Mallinckrodt NELLCOR NPB-4000 Service Manual page 129

Section 13: Microprocessor Computer and Control –Theory of Operation
7FFFF, which is 80000 to FFFFF in bytes. This is the upper portion of the
space. The trend flash is assigned to the 32k byte space above the video ram,
that is, 84000 to 8FFFF words, or 11000 to 14000 bytes. The software, however,
has the ability to overlap the trend flash address with the executable flash
address. The design gives priority to the trend flash address over the executable
flash.
The executable flash has a long delay time for writing to it, and this is why there
are four wait states. It also has a long delay from output data on to output data
float. This requires that data buffers be installed between the 386EX and the
flash. Since doing this only for the flash is awkward, the buffers were put in for
all external devices.
See Figure 13-10. The read cycle time for the executable flash is 110
nanoseconds. The write pulse width must be at least 150 nanoseconds. Refer to
the timing diagrams for the flash for minimum timing parameters.
CLK2
PH2
FLSHCE#
FLSHRD#
In the FPGA control logic, the executable flash chip select, is anded with the
trend flash chip select such that CS2* must be high, inactive, when addressing
the executable flash. This allows the address overlap for the trend flash. The
executable flash chip enable, FLSH1CE#, is generated in the FPGA and then
goes to the executable flash. The trend flash is connected directly to CS2#,
because it has priority over the executable if an overlapping addressing scheme
is used.
See Figure 13-11. The write pulse width is generated via a state machine to give
the proper pulse width.
25NS 25NS
50NS
CLK2
PH2
FLSHCE#
FLSHRD#
25NS 25NS
50NS 50NS
T1 T2W
Figure 13-10: Flash Cycle
50NS 50NS
T1 T2W T2W
Figure 13-11: Write Pulse
50NS 50NS
T2W T2
50NS 50NS
T2W T2
13-15