Real-Time Clock (Rtc) - Mallinckrodt NELLCOR NPB-4000 Service Manual

Section 13: Microprocessor Computer and Control –Theory of Operation
13.10.2 LCD Display RAM
13.10.3 LCD FPGA Control Circuits

13.11 Real-time Clock (RTC)

13-18
Both read and write transfers between the 386EX and the 1351FLB are defined
in the 1351FLB manual, pages 1-33 and 1-34. The timing specifications of the
1351FLB for reading and writing data to and from the control registers or
display RAM, allow a direct interface to the 386EX. External control circuits in
the FPGA are not necessary, except for one signal, the READY# signal. This is
explained in a following section.
The interface signals for the display RAM are prefaced with the letter V, which
indicates video RAM. The interface to the display RAM (VRAM) is defined in
the 1351FLB manual and is connected directly to the RAM.
The LCD display interfaces directly with the 1351FLB. Timing diagrams are in
the associated manuals. The signals used are LCDENB, XSCL, LP, WF, YD,
UD0-UD3, and LD0-LD3. The UD and LD signals are data lines to the upper
and lower display panels. The XSCL is the data shift clock and the LCD display
stores the data on the falling edge of this clock. The LP signal is the latch pulse
and is used to latch the data into the X-drivers. The YD signal is the frame
pulse, which indicates a start-of-frame.
The LCD display chip interfaces directly with the 386EX. The only circuit that
is necessary to generate in the FPGA is the READY# circuit. The 1351
generates a wait signal when transfers are initiated . This wait signal is gated
with the LCD select signals and implements an external READY signal when the
1351 has completed the transfer.
The RTC is a Dallas DS1693, which has the crystal and battery imbedded in the
unit. It is a 28-pin DIP package and runs from a 3.3 volts supply.
CS3# is assigned to the RTC in the I/O space and the software must assign
14 wait states to this unit.
The timing for the DS1693 is shown in Figure 13-12.
See Figure 13-13. The timing for this interface is done in the FPGA. There is a
state machine that is clocked at 20 MHz and generates 18 states.
Figure 13-12: DS1693 Timing