Flash Control - Mallinckrodt NELLCOR NPB-4000 Service Manual

Section 13: Microprocessor Computer and Control –Theory of Operation
13.8.3 DRAM FPGA Circuits

13.9 Flash Control

13.9.1 Executable flash
13-14
RAS#
ROW/COL ADDR
UCAL/LCAS#
Figure 13-9: RAS# and CAS# Requirements
The DRAM control circuits in the FPGA must decode the various 386EX control
signals and generate the DRAM signals. This is done by using CS6# to set a flip
flop when ADS# and PH are true. The flip flop is RAS#. This signal is passed
to two more flip flops and the RAS# output is 75 nanoseconds long. This signal
is generated for all DRAM accesses and refresh. The DRAM output is enabled
when either BLE# or BHE# is true, which means a read is occurring. Since the
DRAM outputs are bi-directional, we need to disable the DRAMOE# signal if a
write is taking place. The WR# signal being false allows DRAMOE# to occur.
If it is true, then the DRAMWR# signal occurs. The BLE# and BHE# signals
are also used to generate the UCAS# and LCAS# signals during a read or write
operation. Since we are using RAS only for refresh, the CAS signals must be
inhibited for refresh.
The flash memory and control consists of two flash chips, a bootable flash (also
called the executable flash) and a trend flash. The control consists of the random
logic in the FPGA. The bootable flash is a 256Kx16 Intel (part no.
E28F400BVT60) or Micron (part no. MT28F400 SG-8) flash with the boot in
the top section (T), and is preprogrammed on the data I/O or some other unit
with the boot program. The executable program can also be programmed this
way or by downloading it to the 386EX via the RS-232 connection. The trend
flash consists of Atmel AT29LV256 32kx8 devices that store the trend data and
that write 64 bytes at a time. It takes two wait states for reading the flash, either
the executable or the trend, and four wait states to write either of these flashes.
The executable flash is a word-oriented flash, that is, reading and writing is done
on a word basis, and byte reads and writes are not allowed. The trend flash is
byte oriented and all reads and writes are done on a byte basis.
The chip select unit has UCS* assigned to the executable flash and CS2* is
assigned to the trend flash. Typically, the executable flash is assigned the upper
256k words, or 512k bytes in the system. The word address space is 40000 to
70NS
10NS 10NS
VALID ROW VALID COL
10NS
20NS
50NS
15NS
20NS