Mallinckrodt NELLCOR NPB-4000 Service Manual page 168

Section 14: Main Color Board Digital Theory of Operation
14.17.3 RAS/ CONTROL CIRCUIT
14.17.3.1 UCAS/ and LCAS/ CONTROL CIRCUITS
14-28
The RAS/ control circuit consists of 5 flip flops called STARTFF, DRAMINFF,
RAS1FF, RAS2FF, and RAS3FF. The ADS/ signal from the 386EX is anded
with the CLK_PH2 signal and then goes to the IDE/ input of the DRAMINFF.
CS6/ (DRAM chip select) goes to the D input. It is clocked into the flip flop on
the rising edge of the IOCLOCK signal at the end of the T1 state (which is the
same as the beginning of the T2 state). At the same time the STARTFF is
conditioned to get set every time CLK_PH2 and ADS/ occur. This signifies the
beginning of a cycle because ADS/ is only true at the beginning of a new cycle.
Once these 2 flip flops are set RAS/ is generated and goes out of the FPGA on
pin 138. CASADREN is low and enables the row address to the DRAM. On the
next 3 consecutive CLK_40MHZ rising edges, RAS1FF is set low, then RAS2FF
is set low, and finally RAS3FF is set low. This takes 75 ns, and when RAS3FF
is set low it disables the RASAND gate and turns off RAS/ (RAS/ goes high).
The STARTFF had to be added because if an idle state occurs after a DRAM
read the RAS state machine does not turn off properly and it will not pick up the
next DRAM read if it follows the idle state. What was happening was as
follows. The DRAMINFF is set at the beginning of the T2 state of a valid
DRAM read cycle. The RAS1FF is set 25 ns later, the RAS2FF is set 25 ns after
that, and the RAS3FF is set 25 ns after that. It takes another 75 ns for each of
these flip flops to turn off and this extends into the first T state of the next cycle.
If it is a valid cycle everything is OK. If, however, it is an idle state, then the
state machine just continues to turn back on because CS6/ remains low during
the idle state even though it' s not doing a DRAM read. Since the state machine
thinks it is back on, it does a DRAM read cycle, but it is out of sync with the
actual next DRAM read. The idle state is only one T state long (50 ns) and the
easiest solution at the time was to put in the STARTFF which turns on only
when ADS/ is true which can only occur at the beginning of a valid cycle and not
when an idle state occurs. The STARTFF turns off when the READY/ signal
occurs which happens at the end of each cycle. This gives a definitive start and
stop for each valid cycle.
25 ns after RAS/ goes low, RAS1FF/ goes low and CASADREN goes low,
enabling the column address to the DRAM. 25ns later RAS2FF/ is set low, and
is conditioned with BLEB/, RAS1/, and LCD_MEM_SEL/ to generate LCAS/.
Substituting BHEB/ for BLEB/ and conditioning with the same signals, UCAS/
is generated. The DRAM is separated into upper and lower portions and require
separate CAS signals, hence the UCAS/ and LCAS/ signals. BLEB and BHEB
are low byte and high byte enable signals from the 386EX. LCD_MEM_SEL/ is
part of the conditioning because software requested that the display memory
might be overlaid with the DRAM memory and, therefore, it has priority.