Dram Control - Mallinckrodt NELLCOR NPB-4000 Service Manual

Section 13: Microprocessor Computer and Control –Theory of Operation
13.7.10 CPU Timing Signals
13.7.11 CPU Signals

13.8 DRAM Control

13.8.1 DRAM Signals
13-12
The 386EX runs from a 40 MHz crystal oscillator and the main timing is derived
from this clock. It is called CLK2. Inside the CPU, CLK2 is divided by two,
generating two new clocks, PH1 and PH2. Each T state is made up of one PH1
and one PH2 clock. There are a minimum of two T states per cycle. Each wait
state is one T state long (50 nanosecond) Therefore, adding wait states is adding
50 nanoseconds for each additional T2 states.
Various signals change at various times within a cycle, and the generic timing is
shown below. Some of the key signals are ADS#, M/IO#, D/C#, W/R#, WR#,
RD#, CS0-CS6#, BLE#, and BHE#. Typical control circuits will look at ADS#
at the end of PH2 and make decisions at this time. See Figure 13-7.
W/R,BLE#,BHE#,CSO:6#,
UCS#,D/C#,M/IO,A1:25
LBA#,READY#
The DRAM control consists of one 256kx16 DRAM chip, three 74ACT157
address mux chips, address resistors, and the FPGA control circuit.
The CS6* (* = # = a low true signal) signal has been assigned to the DRAM
memory address space: 0-3FFFF words, or 0-7FFFF bytes. The CS6* control
register in the chip select unit (CSU) must be programmed for one wait state.
Since the data bus is 16 bits wide and the DRAM is a x16 part, most transfers
will be of the 16-bit variety. However, eight-bit transfers are allowed and
provisions have been made for byte addressing. This is done by using the upper
and lower cas signals, UCAS and LCAS.
For the DRAM design we must generate six signals, RAS#, UCAS#, LCAS#,
DRAMOE#, DRAMWR#, and CASADREN. All of these signals are generated
in the FPGA from the 386EX signals, ADS#, CS6#, M/IO#, D/C#, WR#, and
RD#. Since the CSU is programmed for one wait state, the CSU generates the
READY# signal, which terminates the transfer.
T1 T2 T1
40MHZ
PH1
PH2
ADS#
RD#,WR#
D0:15
Figure 13-7: CPU Signals
T2