Duart Control - Mallinckrodt NELLCOR NPB-4000 Service Manual

Section 14: Main Color Board Digital Theory of Operation

14.10 DUART CONTROL

14-16
The timing diagram above shows the signals and their relationship to each other.
The DUART is a Startech ST16C2550CJ44 which consists of 2 UARTs and
FIFOS for the read and write portions of each UART. Channel 0 is assigned to
the RS-232 port which exits the unit near the AC and DC inputs. Channel 1 is
assigned to the recorder. The FIFOS are 16 bytes deep and transfers to/from the
DUART would save time if done on 8 or 16 byte boundaries.
Interfacing to the DUART is done by assigning CS4# to the DUART I/O space,
with 4 addresses assigned to each UART. The DUART channel 0 is the base
address assigned to CS4# and the channel 1 address is the base address + 8 (A3).
There are 4 addresses assigned to each UART, 0,1,2,and 3.
Software must program 2 wait states for CS4# and define it as a byte device.
A state machine in the FPGA is used to generate the proper signals for
programming the unit.
Figure 14-10: DUART Read/Write Timing
Figure 14-9: Interface Timing