ST STM32H7 Series Programming Manual page 77

PM0214
lowest numbered register using the lowest memory address and the highest number
register using the highest memory address. If the writeback suffix is specified, the value of
Rn + 4 * (n-1) is written back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses
are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers
in reglist. The accesses happen in order of decreasing register numbers, with the highest
numbered register using the highest memory address and the lowest number register using
the lowest memory address. If the writeback suffix is specified, the value Rn - 4 * (n) is
written back to Rn.
The PUSH and POP instructions can be expressed in this form (see
details).
Restrictions
In these instructions:
•
Rn must not be PC.
•
reglist must not contain SP.
•
In any STM instruction, reglist must not contain PC.
•
In any LDM instruction, reglist must not contain PC if it contains LR.
•
reglist must not contain Rn if you specify the writeback suffix.
When PC is in reglist in an LDM instruction:
•
bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch
occurs to this halfword-aligned address.
•
If the instruction is conditional, it must be the last instruction in the IT block.
Condition flags
These instructions do not change the flags.
Examples
LDM R8,{R0,R2,R9}
STMDB R1!,{R3-R6,R11,R12}
Incorrect examples
STM R5!,{R5,R4,R9}
LDM R2, {}
; LDMIA is a synonym for LDM
; value stored for R5 is unpredictable
; there must be at least one register in the list
PM0214 Rev 9
The STM32 Cortex-M4 instruction set
PUSH and POP for
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