ST STM32H7 Series Programming Manual page 232

Core peripherals
UNALIGN_ TRP
Bit 3
Enables unaligned access traps:
0: Do not trap unaligned halfword and word accesses
1: Trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether
UNALIGN_TRP is set to 1.
Bit 2 Reserved, must be kept cleared
USERSETMPEND
Bit 1
Enables unprivileged software access to the STIR, see
(NVIC_STIR) on page
0: Disable
1: Enable.
Bit 0 NONBASETHRDENA
Configures how the processor enters Thread mode.
0: Processor can enter Thread mode only when no exception is active.
1: Processor can enter Thread mode from any level under the control of an EXC_RETURN
value, see
232/262
216:
Exception return on page
PM0214 Rev 9
Software trigger interrupt register
44.
PM0214