ST STM32H747 Manuals

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ST STM32H747 Programming Manual

ST STM32H747 Programming Manual (262 pages)

Brand: ST | Category: Computer Hardware | Size: 2 MB

Table of Contents

Table 1. Applicable Products
1
Table of Contents
2
About this Document

12
The Cortex-M4 Processor

17
The STM32 Cortex-M4 Instruction Set

50
- Instruction Set Summary
  50
- Table 21. Cortex-M4 Instructions
  50
- CMSIS Intrinsic Functions
  58
- Table 22. CMSIS Intrinsic Functions to Generate some Cortex-M4 Instructions
  59
- Table 23. CMSIS Intrinsic Functions to Access the Special Registers
  59
- About the Instruction Descriptions
  60
  - Operands
    60
  - Restrictions When Using PC or SP
    60
  - Flexible Second Operand
    60
  - Shift Operations
    62
  - Figure 13. ASR #3
    62
  - Figure 14. LSR #3
    63
  - Figure 15. LSL #3
    63
  - Figure 16. ROR #3
    64
  - Figure 17. RRX #3
    64
  - Address Alignment
    65
  - PC-Relative Expressions
    65
  - Conditional Execution
    65
  - Table 24. Condition Code Suffixes
    67
  - Instruction Width Selection
    68
- Memory Access Instructions
  69
  - Table 25. Memory Access Instructions
    69
  - Adr
    70
  - LDR and STR, Immediate Offset
    71
  - Table 26. Immediate, Pre-Indexed and Post-Indexed Offset Ranges
    72
  - LDR and STR, Register Offset
    73
  - LDR and STR, Unprivileged
    74
  - LDR, PC-Relative
    75
  - Table 27. Label-PC Offset Ranges
    75
  - LDM and STM
    76
  - PUSH and POP
    78
  - LDREX and STREX
    79
  - Clrex
    80
- General Data Processing Instructions
  81
  - Table 28. Data Processing Instructions
    81
  - ADD, ADC, SUB, SBC, and RSB
    83
  - AND, ORR, EOR, BIC, and ORN
    85
  - ASR, LSL, LSR, ROR, and RRX
    86
  - Clz
    87
  - CMP and CMN
    88
  - MOV and MVN
    89
  - Movt
    91
  - REV, REV16, REVSH, and RBIT
    92
  - SADD16 and SADD8
    93
  - SHADD16 and SHADD8
    94
  - SHASX and SHSAX
    95
  - SHSUB16 and SHSUB8
    96
  - SSUB16 and SSUB8
    97
  - SASX and SSAX
    98
  - TST and TEQ
    99
  - UADD16 and UADD8
    100
  - UASX and USAX
    101
  - UHADD16 and UHADD8
    102
  - UHASX and UHSAX
    103
  - UHSUB16 and UHSUB8
    104
  - Sel
    105
  - Usad8
    106
  - Usada8
    107
  - USUB16 and USUB8
    108
- Multiply and Divide Instructions
  109
  - Table 29. Multiply and Divide Instructions
    109
  - MUL, MLA, and MLS
    110
  - UMULL, UMAAL and UMLAL
    111
  - SMLA and SMLAW
    112
  - Smlad
    114
  - SMLAL and SMLALD
    115
  - SMLSD and SMLSLD
    117
  - SMMLA and SMMLS
    119
  - Smmul
    120
  - SMUAD and SMUSD
    121
  - SMUL and SMULW
    122
  - UMULL, UMLAL, SMULL, and SMLAL
    123
  - SDIV and UDIV
    124
- Saturating Instructions
  125
  - Table 30. Saturating Instructions
    125
  - SSAT and USAT
    126
  - SSAT16 and USAT16
    127
  - QADD and QSUB
    128
  - QASX and QSAX
    129
  - QDADD and QDSUB
    130
  - UQASX and UQSAX
    131
  - UQADD and UQSUB
    132
- Packing and Unpacking Instructions
  134
  - Table 31. Packing and Unpacking Instructions
    134
  - PKHBT and PKHTB
    135
  - SXT and UXT
    136
  - SXTA and UXTA
    137
- Bitfield Instructions
  138
  - Table 32. Instructions that Operate on Adjacent Sets of Bits
    138
  - BFC and BFI
    139
  - SBFX and UBFX
    140
  - SXT and UXT
    141
  - B, BL, BX, and BLX
    142
  - Branch and Control Instructions
    142
  - Table 33. Branch and Control Instructions
    142
  - Table 34. Branch Ranges
    143
  - CBZ and CBNZ
    144
  - TBB and TBH
    147
- Floating-Point Instructions
  149
  - Table 35. Floating-Point Instructions
    149
  - Vabs
    151
  - Vadd
    152
  - Vcmp, Vcmpe
    153
  - VCVT, VCVTR between Floating-Point and Integer
    154
  - VCVT between Floating-Point and Fixed-Point
    155
  - Vcvtb, Vcvtt
    156
  - VDIV
    157
  - Vfma, Vfms
    158
  - Vfnma, Vfnms
    159
  - Vldm
    160
  - Vldr
    161
  - Vlma, Vlms
    162
  - VMOV Immediate
    163
  - VMOV Register
    164
  - VMOV Scalar to Arm Core Register
    165
  - VMOV Arm Core Register to Single Precision
    166
  - VMOV Two Arm Core Registers to Two Single Precision
    167
  - VMOV Arm Core Register to Scalar
    168
  - Vmrs
    169
  - Vmsr
    170
  - Vmul
    171
  - Vneg
    172
  - Vnmla, Vnmls, Vnmul
    173
  - Vpop
    174
  - Vpush
    175
  - Vsqrt
    176
  - Vstm
    177
  - Vstr
    178
  - Vsub
    179
- Miscellaneous Instructions
  180
  - Table 36. Miscellaneous Instructions
    180
  - Bkpt
    181
  - Cps
    182
  - Dmb
    183
  - Dsb
    184
  - Isb
    185
  - Mrs
    186
  - Msr
    187
  - Nop
    188
  - Sev
    189
  - Svc
    190
  - Wfe
    191
  - Wfi
    192
Core Peripherals

193
Revision History

260
- Table 58. Document Revision History
  260

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