Cpuid Base Register (Cpuid) - ST STM32H7 Series Programming Manual

Core peripherals
4.4.2

CPUID base register (CPUID)

Address offset: 0x00
Reset value: 0x410F C241
Required privilege: Privileged
The CPUID register contains the processor part number, version, and implementation
information.
31 30 29 28
Implementer
r r r
15 14 13 12
r r r
Bits 31:24 Implementer: Implementer code
Bits 23:20 Variant: Variant number
The r value in the rnpn product revision identifier
Bits 19:16 Constant: Reads as 0xF
Bits 15:4 PartNo: Part number of the processor
Bits 3:0 Revision: Revision number
The p value in the rnpn product revision identifier, indicates patch release.
224/262
27 26 25
r r r r
11 10 9
PartNo
r r r r
0x41: Arm
0x0: revision 0
0xC24: = Cortex-M4
0x1: = patch 1
24 23 22
Variant
r r r
8 7 6
r r r
PM0214 Rev 9
21 20 19 18
Constant
r r r r
5 4 3 2
Revision
r r r r
PM0214
17 16
r r
1 0
r r