Software Trigger Interrupt Register (Nvic_Stir) - ST STM32H7 Series Programming Manual

Core peripherals
4.3.8

Software trigger interrupt register (NVIC_STIR)

Address offset: 0xE00
Reset value: 0x0000 0000
Required privilege: When the USERSETMPEND bit in the SCR is set to 1, unprivileged
software can access the STIR, see
privileged software can enable unprivileged access to the STIR.
31 30 29 28
15 14 13 12
Reserved
Bits 31:9 Reserved, must be kept cleared.
Bits 8:0 INTID Software generated interrupt ID
Write to the STIR to generate a Software Generated Interrupt (SGI). The value to be written is
the Interrupt ID of the required SGI, in the range 0-239. For example, a value of 0x03 specifies
interrupt IRQ3.
216/262
Section 4.4.6: System control register
27 26 25 24
Reserved
11 10 9 8
w
PM0214 Rev 9
23 22 21 20
7 6 5 4
INTID[8:0]
w w w w
PM0214
(SCR). Only
19 18 17 16
3 2 1 0
w w w w