Auxiliary Control Register (Actlr) - ST STM32H7 Series Programming Manual

Core peripherals
4.4.1

Auxiliary control register (ACTLR)

Address offset: 0x00 (base adress = 0xE000 E008)
Reset value: 0x0000 0000
Required privilege: Privileged
By default this register is set to provide optimum performance from the Cortex-M4
processor, and does not normally require modification. The ACTLR register provides disable
bits for the following processor functions:
• IT folding
•
write buffer use for accesses to the default memory map
• interruption of multi-cycle instructions.
31 30 29 28
15 14 13 12
Reserved
Bits 31:10 Reserved
DISOOFP
Bit 9
Disables floating point instructions completing out of order with respect to integer instructions.
DISFPCA
Bit 8
Disables automatic update of CONTROL.FPCA.
The value of this bit should be written as zero or preserved (SBZP).
Bit 7:3 Reserved
222/262
27 26 25 24
Reserved
11 10 9 8
DISOO DISFP
FP CA
rw rw
PM0214 Rev 9
23 22 21 20
7 6 5 4
PM0214
19 18 17 16
3 2 1 0
DISFOL DISDE DISMC
D FWBUF YCINT
rw rw rw