ST STM32H7 Series Programming Manual page 220

Core peripherals
Offset Register
NVIC_IABR1
0x304
Reset Value
: :
NVIC_IABR7
0x31C
Reset Value
NVIC_IPR0
0x400
Reset Value
NVIC_IPR1
0x404
Reset Value
: :
NVIC_IPR59
0x4EC
Reset Value
NVIC_STIR
0xE00
Reset Value
220/262
Table 49. NVIC register map and reset values (continued)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
- - - - - - - -
IP[3]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IP[7]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IP[239]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ACTIVE[63:32]
:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IP[2]
IP[6]
:
IP[238]
SCB registers
Reserved
Reserved
PM0214 Rev 9
ACTIVE [239:224]
IP[1]
IP[5]
IP[237] IP[236]
INTID[8:0]
0 0 0 0 0 0 0 0 0
PM0214
IP[0]
IP[4]