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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.2 Non-Maskable Interrupt
The non-maskable interrupt is accepted unconditionally, even when interrupts are disabled (DI states) in the
interrupt disabled (DI) status. The NMI is not subject to priority control and takes precedence over all the other
interrupts.
The non-maskable interrupt request is input from the NMI pin. When the valid edge specified by bit 0 (ESN0) of
the external interrupt mode register 0 (INTM0) is detected on the NMI pin, the interrupt occurs.
While the service routine of the non-maskable interrupt is being executed (PSW.NP = 1), the acceptance of another
non-maskable interrupt request is kept pending. The pending NMI is accepted after the original service routine of
the non-maskable interrupt under execution has been terminated (by the RETI instruction), or when PSW.NP is cleared
to 0 by the LDSR instruction. Note that if two or more NMI requests are input during the execution of the service
routine for an NMI, the number of NMIs that will be acknowledged after PSW.NP goes to "0", is only one.
The operation at the execution of pending non-maskable interrupt request differs depending on the V854 operation
mode.
(1) In single-chip mode
The operation is returned to the main routine once and at least one instruction in the main routine is executed
between the end of the first non-maskable interrupt processing and the start of the pending non-maskable
interrupt processing.
(2) In ROM-less mode
The pending non-maskable interrupt processing starts following the end of the first non-maskable interrupt
processing. The operation is not returned to the main routine.
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User's Manual U11969EJ3V0UM00
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