NEC V854 UPD703006 User Manual page 410

CC3PR00 to CC3PR02 ........................................ 116
CCLR0 ................................................................... 168
CE .......................................................................... 297
CE0 ....................................................................... 166
CE1 ....................................................................... 169
CE20 to CE24 ....................................................... 170
CE3 ....................................................................... 171
CESEL ................................................................... 142
CG ........................................................................... 29
CKC ....................................................................... 137
CKDIV0 to CKDIV1 ............................................... 137
CKSEL ..................................................................... 44
CL .......................................................................... 210
CL0, CL1 ............................................................... 241
CLD ....................................................................... 241
CLE ....................................................................... 154
clear/start of timer (timer 0) ................................. 177
clear/start of timer (timer 1) ................................. 185
clear/start of timer (timer 2) ................................. 189
clear/start of timer (timer 3) ................................. 193
CLKOUT .................................................................. 44
CLKOUT signal output control ............................. 152
CLO ......................................................................... 43
CLO signal output control .................................... 153
clock control register ............................................ 137
clock generation function ..................................... 135
clock generator ....................................................... 29
clock output control .............................................. 165
clock output inhibit ....................................... 140, 152
clock output mode register ................................... 154
clock serial interface 0 to 3 .................................. 220
clock serial interface mode register 0 to 3 .......... 222
CLOM .................................................................... 154
CLSn0, CLSn1 (n = 0 to 3) .................................. 223
CM10, CM11, CM10L, CM11L ............................. 163
CM1IC0, CM1IC1 ................................................. 116
CM1IF0, CM1IF1 .................................................. 116
CM1MK0, CM1MK1 .............................................. 116
CM1PRn0 to CM1PRn2 (n = 0, 1) ....................... 116
CM20 to CM24 ...................................................... 164
CM2IC0 to CM2IC4 .............................................. 116
CM2IF0 to CM2IF4 ............................................... 116
CM2MK0 to CM2MK4 ........................................... 116
CM2PRn0 to CM2PRn2 (n = 0 to 4) ................... 116
CMS00 to CMS03 ................................................. 167
CMS3 .................................................................... 171
COI ........................................................................ 239
command register ................................................... 78
410
APPENDIX C INDEX
communication command .................................... 393
communication reservation .................................. 273
compare operation (timer 0) ................................ 181
compare operation (timer 1) ................................ 187
compare operation (timer 2) ................................ 189
compare operation (timer 3) ................................ 194
compare register 10, 11 ....................................... 163
compare register 20 to 24 .................................... 164
conflict of signals .................................................. 388
count clock selection (timer 0) ............................. 175
count clock selection (timer 1) ............................. 183
count clock selection (timer 2) ............................. 188
count clock selection (timer 3) ............................. 192
count operation (timer 0) ...................................... 174
count operation (timer 1) ...................................... 183
count operation (timer 2) ...................................... 188
count operation (timer 3) ...................................... 192
CP10 to CP13, CP10L to CP13L ........................ 162
CP3 ....................................................................... 165
CPU ......................................................................... 29
CPU address space ........................................ 56, 58
CPU function ........................................................... 49
CPU register set ..................................................... 50
CRXE0 to CRXE3 ................................................. 222
CS .......................................................................... 297
CS1 ....................................................................... 169
CS20 to CS24 ....................................................... 170
CS3 ....................................................................... 171
CSI0 to CSI3 ......................................................... 220
CSIC0 to CSIC3 ................................................... 116
CSIF0 to CSIF3 .................................................... 116
CSIM0 to CSIM3 ................................................... 222
CSMK0 to CSMK3 ................................................ 116
CSOT0 to CSOT3 ................................................. 222
CSPRn0 to CSPRn2 (n = 0 to 3) ......................... 116
CTXE0 to CTXE3 ................................................. 222
CV ........................................................................ 45
DD
CV ........................................................................ 45
SS
CY ............................................................................ 53
[D]
DAD ....................................................................... 241
data space ................................................. 58, 69, 97
data wait control register ........................................ 86
DCLK0, DCLK1 ..................................................... 142
DFC ....................................................................... 241
diagram of processing status ............................... 141
direct mode ........................................................... 136
User's Manual U11969EJ3V0UM00