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Throughout
Deletion of BV
Modification of voltage of V
Addition of µ PD703006 to the target devices
p.44
Modification of description in 2.3 (19) MODE0 to MODE2 (Mode 0 to 2)
p.47
Modification of recommended connection method for pins P40/AD0 to P47/AD7, P50/AD8
to P57/AD15, P60/A16 to P67/A23, P90/LBEN/WRL, P91/UBEN, P92/R/W/WRH, P93/
DSTB/RD, P94/ASTB, P95/HLDAK, P96/HLDRQ, WAIT, and MODE0 to MODE2 in 2.4
Pin I/O Circuit Type and Connection of Unused Pins
p.53
Modification of description of EP flag in Figure 3-3 Program Status Word (PSW)
p.54
Modification of description in 3.3.2 Specifying operation mode
p.140
Addition of Caution in 6.5.1 (2) IDLE mode
p.140
Modification of description in 6.5.1 (3) (a) PLL mode
p.140
Modification of description in 6.5.1 (3) (b) Direct mode
p.142
Modification of description of CESEL bit in 6.5.2 (1) Power save control register (PSC)
p.149
Modification of description in 6.6 (1) Securing time using internal time base counter
(NMI pin input)
p.150
Modification of description in 6.6 (2) Securing time by signal level width (RESET pin
input)
p.159
Addition of Note in 7.2 (1) Timer 0 (24-bit timer/event counter)
p.161
Addition of description in 7.2.1 (1) Timers 0, 0L (TM0, TM0L)
p.206
Addition to the item Transfer rate in 8.2.1 Features
p.220
Addition to the item High transfer speed in 8.3.1 Features
p.241
Addition of Note to bits 4 and 5 in 8.4.4 (3) IIC clock selection register (IICCL)
p.242
Addition of Caution to 8.4.4 (4) IIC shift register (IIC)
p.276
Addition of 8.4.6 (15) (b) Operation during communication reservation (when a multi-
master is used), (c) Start operation after communication reservation (when a multi-
master is used), and (d) STT setting timing (when a multi-master is used)
p.299
Modification of description of function of bits FR2 to FR0 in the table in 9.3 (2) A/D
converter mode register 1 (ADM1)
p.301
Modification of setting value of ADM1 register in the table of operation and trigger modes
in 9.4.2 Operation mode and trigger mode
pp.308 to 310,
Addition of Tables 9-1 to 9-9 and Figures 9-6 to 9-14
312 to 318
p.319
Modification of description in 9.8.2 Interval of the external/timer trigger
p.379
Addition of description in 13.2 (2) Power-ON reset
p.380
Modification of initial values after reset of timer registers (TM0, TM1, TM0L, TM1L, TM20
to TM24, TM3) in Table 13-2 Initial Values after Reset of Each Register (1/2)
p.384
Deletion of CSI2 in 14.3 Programming Environment
p.385
Deletion of CSI2, SO2, SI2, and SCK2 in 14.4 Communication System
p.388
Deletion of CSI2 and the pin used by CSI2 in the table of pins used by each serial
interface in 14.5.2 Serial interface pin
p.392
Deletion of CSI2 in Table 14-1 List of Communication Systems
p.393
Modification of the table of flash memory control commands in 14.6.4 Communication
command
6
Major Revisions in This Edition
and BV
DD
SS
PP
The mark
shows major revised points in this edition.
User's Manual U11969EJ3V0UM00
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