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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
INTC accepted
CPU processing
The INT input masked by the interrupt controllers and the INT input that occurs while the other interrupt is being
processed (when PSW.NP = 1 or PSW.ID = 1) are internally pended by the interrupt controller. When the interrupts
are unmasked, or when PSW.NP = 0 and PSW.ID = 0 by using the RETI and LDSR instructions, the pending INT
input starts the new maskable interrupt processing.
110
Figure 5-5. Maskable Interrupt Processing
INT input
XXIF = 1
Yes
XXMK = 0
Yes
Priority higher than
that of interrupt currently
processed?
Yes
Priority higher
than that of other interrupt
request?
Yes
Highest default
priority of interrupt requests
with same priority?
Yes
Maskable interrupt request
PSW. NP
0
PSW. ID
0
←
EIPC
restored PC
←
EIPSW
PSW
←
ECR. EICC
exception code
←
PSW. EP
0
←
1
PSW. ID
←
PC
vector address
Interrupt processing
User's Manual U11969EJ3V0UM00
No
Interrupt request?
No
Interrupt unmasked?
No
No
No
Interrupt request pending
1
1
Interrupt process pending
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