Table of Contents
Advertisement
CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.5.3 Restore
To restore or return execution from the exception TRAP, the RETI instruction is used.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
(1) Restores the restored PC and PSW from EIPC and EIPSW because the EP bit of PSW is 1.
(2) Transfers control to the restored PC address and PSW status.
Figure 5-13 illustrates the processing of the RETI instruction.
1
Caution
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the
exception trap process, in order to restore the PC and PSW correctly during recovery by the
RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction
immediately before the RETI instruction.
Remark
The solid line shows the CPU processing flow.
130
Figure 5-13. RETI Instruction Processing
RETI instruction
PSW.EP
0
PSW.NP
0
← EIPC
PC
← EIPSW
PSW
Original processing restored
User's Manual U11969EJ3V0UM00
1
← FEPC
PC
← FEPSW
PSW
Advertisement
Table of Contents
