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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.3.7 Noise elimination
INTP, TI, TCLR, and ADTRG pins are attached with respective digital noise elimination circuit. Thereby, the input
levels of these pins are sampled at each sampling clock (f
times consecutively, the input pulse is eliminated as a noise.
The noise elimination time for each pin is shown below. The sampling clock of INTP30 pin can be selected from
φ, φ/64, φ/128, or φ/256. For the settings, write values to INTM7 register (refer to 5.3.8 (2) (a) External interrupt
request register 7 (INTM7)).
INTP00 to INTP03
TCLR0/INTP04
TI0/INTP05
INTP10 to INTP13
TI1/INTP14
TI20/INTP20 to TI24/INTP24
ADTRG
INTP30
Remark f
f
SMP
Input signal
3 clocks max.
Internal signal
Rising edge
detected
Falling edge
detected
Notes 1. Unrecognizable noise pulse width
2. Recognizable signal pulse width
Pin
f
SMP
φ
φ
φ
φ
φ
φ
φ
φ
φ /64
φ /128
φ /256
: Sampling clock
SMP
φ
: Internal system clock
Figure 5-9. Example of Noise Elimination Timing
Note 2
Note 1
2 clocks min.
User's Manual U11969EJ3V0UM00
). As a result, if the same level cannot be detected three
SMP
Noise Elimination Time
2 to 3 system clocks
2 to 3 system clocks
128 to 192 system clocks
256 to 384 system clocks
512 to 768 system clocks
119
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