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(9) Address coincidence detection
The I
2
C bus can select the specific slave device when the master transmits the slave address.
Address coincidence detection can be automatically performed by hardware. If the local address is set to the
slave address register (SVA), INTIIC interrupt request generates only when the slave address transmitted from
the master and the address set in SVA coincide or when an extension code is received.
(10) Error detection
2
The I
C bus can detect transmission errors by comparing the IIC data before transmission starts and that after
transmission ends because the status of the serial bus during transmission (SDA) is captured also to IIC shift
register (IIC) of the transmitting device. In this case, if the two data differ, it is judged that a transmission error
has occurred.
(11) Extension code
(a) Interrupt request (INTIIC) is issued at the fall of the eighth clock by setting the extension code reception
flag (EXC) regarding it as reception of exception code when the higher 4 bits of the reception address
is either "0000" or "1111".
The local address stored in the slave address register (SVA) is not affected.
(b) The following is set when "111110xx" is set to SVA by 10-bit address transfer and "111110xx0" is
transferred from the master. However, interrupt request (INTIIC) generates at the fall of the eighth clock.
• Coincidence of the higher 4-bit data : EXC = 1
• Coincidence of the 7-bit data
(c) The processing after interrupt request is issued differs depending on the data following the extension code.
Therefore, it is performed by software.
For example, LREL is set to 1 and the next communication wait status enters not to operate a device as
a slave after receiving extension code.
Slave Address
0000 000
0000 000
0000 001
0000 010
1111 0xx
(12) Arbitration
When more than one master simultaneously output start conditions (when setting STT =1 before STD = 1 is
set), master communication continues until the data differs while adjusting the clock. This operation is called
arbitration.
The master which is defeated in arbitration sets the ALD bit of the IIC status register (IICS) at the timing at
which the master is defeated in the arbitration, sets both SCL and SDA lines in Hi-Z status, and releases bus.
The arbitration defeat is detected by software when ALD =1 at the next interrupt request generation timing
(the eighth or ninth clock, stop condition detection, etc.).
For the interrupt generation timing, refer to (7) I
CHAPTER 8 SERIAL INTERFACE FUNCTION
: COI = 1
Table 8-4. Definition of Extension Code Bit
R/W Bit
0
General call address
1
Start byte
x
CBUS address
x
Address reserved for different bus format
x
10-bit slave address specification
2
C interrupt (INTIIC).
User's Manual U11969EJ3V0UM00
Description
271
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