NEC V854 UPD703006 User Manual page 223

Bit Position Bit Name
1, 0 CLSn1, CLSn0
Remark n = 0 to 3
Caution Set the CLSn1 and CLSn0 bits, in the transmission/reception disable state (CTXEn bit = CRXEn
bit = 0). If these bits are set in a state other than transmission/reception disabled, normal
operation is not guaranteed.
(2) Serial I/O shift register 0 to 3 (SIO0 to SIO3)
These registers convert 8-bit serial data into parallel data, and vice versa. The actual transmitting and receiving
of data is performed by writing data to and reading data from the SIOn registers.
A shift operation is performed when CTXE = "1" or CRXE = "1".
These registers can be read/written in 8- or 1-bit units.
7 6
SIO0 SIO07 SIO06
SIO1 SIO17 SIO16
SIO2 SIO27 SIO26
SIO3 SIO37 SIO36
Bit Position Bit Name
7 to 0 SIOn7 to
SIOn0
(n = 0 to 3)
CHAPTER 8 SERIAL INTERFACE FUNCTION
Clock Source
Specifies serial clock.
CLSn1 CLSn0
0 0 External clock
0 1 Internal clock
1 0
1 1
Notes 1. For setting of BPRMn register, refer to section 8.5 Baud Rate Generator 0 to 3
(BRG0 to BRG3).
2. φ /4 and φ /2 indicate dividing signals ( φ : internal system clock).
5 4 3
SIO05 SIO04 SIO03 SIO02
SIO15 SIO14 SIO13 SIO12
SIO25 SIO24 SIO23 SIO22
SIO35 SIO34 SIO33 SIO32
Serial I/O
Data is shifted in (received) or out (transmitted) from MSB or LSB side.
User's Manual U11969EJ3V0UM00
Function
Specifies Serial Clock
Specified by BPRMn register
φ /4
Note 2
φ /2
Note 2
2 1 0
SIO01 SIO00
FFFFF08AH
SIO11 SIO10
FFFFF09AH
SIO21 SIO20
FFFFF0AAH
SIO31 SIO30
FFFFF0BAH
Function
SCKn pin
Input
Note 1 Output
Output
Output
Address After reset
Undefined
Address After reset
Undefined
Address After reset
Undefined
Address After reset
Undefined
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