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Figure No.
3-1.
Program Counter (PC) ................................................................................................................ 51
3-2.
Interrupt Source Register (ECR) ................................................................................................ 52
3-3.
Program Status Word (PSW) ..................................................................................................... 53
3-4.
CPU Address Space ................................................................................................................... 56
3-5.
Image on Address Space ........................................................................................................... 57
3-6.
External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes) ................................... 64
3-7.
External Memory Area (when expanded to 4 Mbytes) .............................................................. 65
3-8.
External Memory Area (when fully expanded) ........................................................................... 66
3-9.
Recommended Memory Map ...................................................................................................... 70
4-1.
Example of Inserting Wait States ............................................................................................... 87
5-1.
Non-Maskable Interrupt Processing ......................................................................................... 103
5-2.
Accepting Non-Maskable Interrupt Request ............................................................................ 104
5-3.
RETI Instruction Processing ..................................................................................................... 105
5-4.
Block Diagram of Maskable Interrupt ....................................................................................... 108
5-5.
Maskable Interrupt Processing ................................................................................................. 110
5-6.
RETI Instruction Processing ..................................................................................................... 111
5-7.
Example of Interrupt Nesting Process ..................................................................................... 113
5-8.
Example of Processing Interrupt Requests Simultaneously Generated ................................ 115
5-9.
Example of Noise Elimination Timing ...................................................................................... 119
5-10.
Software Exception Processing ................................................................................................ 126
5-11.
RETI Instruction Processing ..................................................................................................... 127
5-12.
Exception Trap Processing ....................................................................................................... 129
5-13.
RETI Instruction Processing ..................................................................................................... 130
5-14.
Pipeline Operation at Interrupt Request Acknowledge (General Description) ....................... 133
6-1.
Block Configuration ................................................................................................................... 151
6-2.
CLO Signal Output Timing ........................................................................................................ 153
7-1.
Basic Operation of Timer 0 ....................................................................................................... 174
7-2.
Operation after Occurrence of Overflow (when ECLR0 = 0, OST0 = 1) ............................... 176
7-3.
Clearing/Starting Timer by TCLR0 Signal Input
(when ECLR0 = 1, CCLR0 = 0, OST0 = 0) ............................................................................. 177
7-4.
Relations between Clear/Start by TCLR0 Signal Input and Overflow
(when ECLR0 = 1, OST0 = 1) .................................................................................................. 178
7-5.
Clearing/Starting Timer by CC03 Coincidence (when CCLR0 =1, OST0 = 0) ...................... 178
7-6.
Relations between Clear/Start by CC03 Coincidence and Overflow Operation
(when CCLR0 = 1, OST0 = 1) .................................................................................................. 179
7-7.
Example of TM0 Capture Operation ........................................................................................ 180
7-8.
Example of TM0 Capture Operation (when both edges are specified) .................................. 180
7-9.
Example of Compare Operation ............................................................................................... 181
16
LIST OF FIGURES (1/4)
Title
User's Manual U11969EJ3V0UM00
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