Table of Contents
Advertisement
CHAPTER 7 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) External count clock
The signal input to the TI1 pins is counted. At this time, timer 1 operates as an event counter.
To set an external count clock, see the table below.
PRM13
The valid edge of TI1 is specified by the ES bits of the INTM3 register.
7.5.3 Overflow
If overflow occurs as a result of counting the TM1 register count clock frequency to FFFFFFH, a flag is set to the
OVF1 bits of the TOVS register, and an overflow interrupt (INTOV1) is generated.
The value of the OVF1 flag is retained until it is changed by user application.
The operation of the TM1 register after occurrence of overflow is determined by the OST1 bit.
(1) Operation after occurrence of overflow when OST1 = 0
The TM1 register continues counting.
(2) Operation after occurrence of overflow when OST1 = 1
TM1 = 000000H is retained, and the TM1 register stops counting. At this time TM1 stops with CE1 = 1. Perform
the following to resume counting.
• Write 1 to CE1 bit
• Write 1 to CS1 bit
The operation is not affected even if the CE1 bit is set to 1 during count operation.
184
PRM12
PRM11
1
1
1
ES141
ES140
0
0
Falling edge
0
1
Rising edge
1
0
RFU (reserved)
1
1
Both rising and falling edges
User's Manual U11969EJ3V0UM00
PRM10
External Count Clock
1
TI1 input
Valid Edge
Advertisement
Table of Contents
